Generating Data on Rising edge clock using FPGA

[Mshaltout]

I have an 7820 R series digital IO FPGA and i am working on a project where i have a clock running at @ 4Mhz. What i want is every rising edge of the clock, i generate a signal. the problem lies where the data generated is after the rising edge with 1us which means it will take 4 clock cycles to generate a signal as shown in the attached image. Is there a way to generate a signal which is synced with the rising edge.   

[Mshaltout]

I have an 7820 R series digital IO FPGA and i am working on a project where i have a clock running at @ 4Mhz. What i want is every rising edge of the clock, i generate a signal. the problem lies where the data generated is after the rising edge with 1us which means it will take 4 clock cycles to generate a signal as shown in the attached image. Is there a way to generate a signal which is synced with the rising edge.  

[crossrulz]

Start by having your output data calculated while you are waiting for the edge.  Then move all of the extra stuff to after you write to the output (your counter).  Actually, since you know how many iterations you are going to perform, you really should just make that a FOR loop and it eliminates the need for you to add your own counter.

[Mshaltout]

First of all thank you for your reply.

I tried to buffer a Digital IO input @4mhz to another Digital IO output. When i measure both signals there is a delay of 1us between the rising edge of the original signal and the rising edge of the output signal, and that is with straight forward connection without any processing on the signal. At 4Mhz that is a big issue, because the output signal delays 4 cycles than the original one. Is there any solution where the delay does not exceed 25ns as illustrated in NI support.