FlexRIO API transferring data between fpga and host

[IhmeKyselijä]

Hi,

I am wondering how the data streaming works from my PXIe-5774 to the host computer on the getting started example program. I can see from the FPGA code that the data is sent to two FIFOs (as per usual) seen in this screencap of the example code that you can get from (Hardware input and output -> FlexRIO -> Integrated IO -> Getting Started):

(Yes I can read what it says on the comment on the loop)

On the host side though I don't see a similar fifo but instead I see a call library function node.

I understand that the stream instance controls to which instance the data is sent and where it comes out but I tried to change the fifos on the FPGA side to stream.to host 1.0 and 1.1 and the instance on the host code to 1 but labview gives me an error (labview fpga Attribute is undefined or not present in the currently running session. Property: Stream Finite Channel Name: 1). Can I change the FIFO settings on the project and can I create new fifos for the same instance or for a different instance? How is this accomplished? How does this streaming work in general?

Just very confused about this FlexRIO FPGA stuff... Thanks
Aarni

[wiebe@CARYA]

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@IhmeKyselijä wrote:

Just very confused about this FlexRIO FPGA stuff... Thanks
Aarni

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Me too. (no hashtag)

It's been a while since I used a FlexRIO and never knew about the session stuff (could be too new).

AFAIK, the FlexRIO FIFOs are the same as the normal FPGA FIFOs, and\or vice versa.

Have you tried a normal (simple) FIFO example?

[IhmeKyselijä]

I tried a program that was just sending numbers to a target to host fifo but I was unable to read data from the fifo on the host side... It is very limiting to have to use exactly that fifo arangement to get data to the host... It is very slow to "try" stuff since the compilation times are so slow.

[wiebe@CARYA]

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@IhmeKyselijä wrote:

It is very limiting to have to use exactly that fifo arangement to get data to the host...

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Well, I never used that arrangement.

If it doesn't work, then it would indeed be very limiting.

@IhmeKyselijä wrote:

It is very slow to "try" stuff since the compilation times are so slow.

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The FPGA side is pretty standard. If this doesn't change, you don't need to recompile.

It's the host side that completely alien to me.

If you use a string FPGA reference you should be able to access the FIFO directly. I'm sure there are examples for that. Sorry, don't have any FPGA HW or SW atm. 

EDIT: this is hard to find online... I'd try to use FIFO.Configure (Invoke Method) - NI, FIFO.Read (Invoke Method) - NI, FIFO.Start (Invoke Method) - NI, etc.

EDIT2: Here's more what I had in mind (and always worked for me, even on a FlexRIO: Taking Your First Measurement in LabVIEW FPGA (Data Logging) - NI

[UMASO]

It may be better for you not to use FlexRIO API on host-side.  FlexRIO API on host-side is not necessary.  Read/Write control and FPGA method node can replace almost all of FlexRIO API except the ones like setting reference clock, etc which accesses non-diagram stuffs.  

[IhmeKyselijä]

Hi,

I don't understand how the FIFOs are supposed to be arrange. I read the article an I think I did what I was supposed to but... No data to host.

How am I supposed to configure the FIFO stuff so that it work?

This project is just for test purposes so that I can see that sending data by FIFO normally is an option.

I have tried many different arrangements of those nodes on the host side and this arrangement is just the most recent

I have attached all the project files below.

Thanks:

Aarni

[wiebe@CARYA]

You're setting up the fifo every iteration of the while loop.

Do the setup once (move it before the loop) and do (only) the read in a loop.

[IhmeKyselijä]

Okay. Yes I am very new to this... What is wrong with this block diagram then. I am still not receiving any output...

Aarni

[wiebe@CARYA]

With Wait Until Done? set to true the loop will never start.

Turn on execution highlighting to understand.

So, set it to false. 

[IhmeKyselijä]

Even when that is set to false it will still not receive data. The host goes to the while loop but the fifo doesn't have any data...