Fixed Point Typedef on an FPGA Target comes up as Extended Precison

[John_Neutron]

I have a typedef FXP control in an FPGA project. 

When I insert the typedef control into an FPGA VI then I notice that although the representation is correct on the front panel, when I view the properties for the control on the block diagram, it comes up as an extended precision type.

This is fine for connecting sub-VIs etc together but it means that when I try and connect this type into an IP integration block, I get a coercion dot.

The FXP type I have set is 24 bit long (24 bit integer) and ensured that the typedef is in the FPGA branch of the project.

LabVIEW version; Professional Development System 10.0f2

Any help or sugegstions would be greatly appreciated.

Cheers

John

[alpha1]

Hi John,

I've tried to replicate the bug you are seeing in the same version of LabVIEW and can verify that I've seen the same problem. The issue seems to be the same for a normal VI and not just under an FPGA target. I have filed a bug report to R&D on this issue, and for reference the ID is CAR#257825.