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FPGA time

Hi,

 

I am using FPGA. I have while loop and inside the while loop I have case-structure with three cases. Everytime I choose some case I want the real time starting from 0. I need this time in case. Any idea how I can do it?

 

BR

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Message 1 of 10
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Hi WatFin,

 

Everytime I choose some case I want the real time starting from 0. I need this time in case. Any idea how I can do it?

Please explain "realtime"…

How is this problem related to FPGA?

 

3 simple steps:

1. Store the "time" in a shift register.

2. Wire through your case structure.

3. Set the value to zero when you think it is needed to do so…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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What exactly do you mean by the "real time"?

 

You can set a separate timed while loop based off the 40 MHz clock and increments an indicator by 1 every iteration.  Read the indicator with a local variable and you'll have how many clock ticks have passed.

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Message 3 of 10
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Ok, what is real time? I hvae crio with 40 MHz and my loop sould work 2,48 kHz. The real-time I meant is the time we use to look at.

Could you show me basic example please?

 

 

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Hi WatFin,

 

put a (RealTime) wait in your loop set to 16129 ticks (of your default 40MHz clock) to have it iterate at ~2.48kHz…

 

The real-time I meant is the time we use to look at.

What are you "looking at"? ("Real-time")

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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@WatFin wrote:

real time


Just to clarify this thread: You so-to-say want to program a stop-watch that starts counting from 00:00:00 again every time you "press" the reset case. Is this the "real time" you mean?

 


Ingo – LabVIEW 2013, 2014, 2015, 2016, 2017, 2018, NXG 2.0, 2.1, 3.0
CLADMSD
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Yep that I want to do. The real-time is the clock time 0 1 2 3.. etc

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Hi WatFin,

 

you still can count clock cycles/ticks/iterations of your loop in the FPGA: just scale that number later on to your desired timebase of seconds (or ms)…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 8 of 10
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I am communicating with FPGA and RT. Code for Pulse generation (for 100KHz freq i.e. 10usec - 400 ticks)  is written in FPGA. But in RT using this FPGA code I'm not getting the same frequency. I am getting only 70 ticks instead of 400 ticks. Help me in solving this..

 

Thank You 

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Message 9 of 10
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I am communicating with FPGA and RT. Code for Pulse generation (for 100KHz freq i.e. 10usec - 400 ticks)  is written in FPGA. But in RT using this FPGA code I'm not getting the same frequency. I am getting only 70 ticks instead of 400 ticks. Help me in solving this..

 

Thank You 

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Message 10 of 10
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