FPGA synchronization between two timed loops

[Harlequinade]

First of all, I appreciate the forums here very much and have read many interesting topics. This is the first time I can't solve it with the search and hope for your input.

Information:

I'm using LabVIEW 2009 f3, PXI-1033 with the PXI-7813R.

Problem:
In my FPGA program I have two loops, where one needs to run as fast as possible (A) and the second just fast (B). A runs at 40 MHz and B at 20 MHz. These are for both loops limiting speeds. B can't run faster and A should not run slower.
Loop A captures sensory information and integrates the data as many loops as indicated by the user. When finished it needs to send a trigger to B, which calculates new position information and sends it to the machine. Only at certain moments B needs to perform something and is silent for the rest of the time.

I thought of two ways, but neither work for me.

i) using a boolean trigger. As in one loop the boolean from A can become true and switches the next loop to false, B doesn't capture all the triggers and has a 50% chance of getting the triggers and is thus not optimally synchronized. 

ii) using occurrences. It sounds very interesting, but these are forbidden between differently timed loops.

I played with many scenarios, but can't figure out a proper one. Has anyone some suggestions?

[gsussman · Accepted solution]

This appears to be a fairly straight forward Producer/Consumer type scenario.

I would use a device scoped FIFO to transfer data from the producer loop (top) to the consumer loop (bottom).

Depending on how often the producer generates data (every cycle or every Nth cycle?) the case structure around the FIFO write will allow it to write only when your required conditions are met.

The consumer loop reads from the FIFO with a timeout of "0". When the FIFO times out, the consumer runs the case that does nothing. When the FIFO does not time out, the case that processes the data and sends it to the Windows side runs.

In my example I used 2 case structures to illustrate the two different modes. In your code, you should use a single case structure.

On the FPGA, there is no advantage to putting a loop to "sleep" while no data exists. Because you are running in hardware and not allocating the cycles of the CPU these loops can run concurrently with no increase in latency of either

[Harlequinade]

Great! This solved my problem.