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FPGA parallel loops

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Is there a way tyo get  2 pieces of code to run simutaneously on a PXI7853R??

I want to output a 1 MHz clock on one line and then after 8 clock cycles out put a chip select.  I tried it in a do while loop but when I look at it on a scope it looks like the clock stops outputting  when the chip select starts then the clock starts again when the chip select code is done.



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Is is another one I tried..It works...a little better.



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LabVIEW's dataflow semantics enforce that each iteration of the loop not complete until ALL the code within the loop diagram complete. Since you have two separate data paths that take a different amount of time (the top and bottom sequence structures), the two pieces of code will essentially kept in line with one another.


If you want the two pieces of code to run independently, you'll want to put them in their own loops so they are free to run at their own rates.

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Accepted by clint100

Do not make separate loops for this... bad.


For protocols like this you want to define the base clock you will need (1MHZ in your case), and create state-machine-style logic to assert the lines accordingly. For your example, don't hardcode a 40 tick wait between the edges of the DIN (That is what makes it look like it stops... the only thing the previous poster even helped with). Instead make DIN hit an edge after 2 iterations of the 20-tick clock. Think of it as 2 iterations high:2 iterations low. It will require more logic outside the case structure that holds DIN, not a parallel loop. You do it like this because parallel while loops can get out of synch for various reasons. You start cranking the clock speed, changing arbitration options, puting logic in some case structure that exceeds your loop timer. All (as you are experiencing) are bad for digital protocols. 


In the end, the best way is to use a single cycle timed-loop with a case structure (i.e. SCTL State-machine) for logic like this. The end of this whitepaper introduces the concept: and the next in the series goes in depth

Message 4 of 6

kuhlmanation is correct. When I first read your post (and the title), I thought you were trying to generate two distinct signals at two distinct rates. I didn't notice the intended correlation.



If the signals are related, then you'll want to create a derived clock at the lowest common clock rate that hits each cycle you need to make a transition. You can then set your Single-Cycle Loop to use that clock and then have the state machine transition your signals on the appropriate cycles.

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