FPGA number of logical LUT blocks exceeds the capacity for the target device

[wojtek432]

Hello,

I'm trying to implement Fuzzy type-2 controler on FPGA in sbRIO 9636.

When I'm simulating my logic on PC it works properly, but not fast enought, so I'm trying to run it on FPGA, but then I'm getting error on compilation.

I'm including error message, and screenshot from compilation with SCTL, also I'm enclosing 2 projects- one is with SCTL, and second with normal loop. Of course the second one has got less complicated logic, because it doesn't send me errors, when I'm using iteration number in for loop.

My question is what can I do, to reduce some memory, to make program to compile?

Maybe I'm making some basic mistakes, which cost me a lot of memory?

Spoiler

ERROR:Pack:2412 - The number of logical LUT blocks exceeds the capacity for the target device.
ERROR:Pack:2860 - The number of logical carry chain blocks exceeds the capacity for the target device. This design requires 23172 slices but
only has 3411 slices available that allow carry chains.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.

 And also I've got one more question. On compilation log I can see also that I used 0/116, and 0/58 Block RAMs, and DSP48s. Is there a possibility that I can move part of my logic, to these places?

[wiebe@CARYA]

If you want to do stuff with this level of complexity, you might consider to make your code a bit cleaner. If you want us to look at it, this is more or less a requirement. It's not often Diagram Clean Up makes things better.

maxvalue.vi and minvalue.vi seem a bit silly. Array Min & Max work on FPGA, but at least use Max & Min in stead of the compare and selector.

A lot of the data (baza regul?) seem to be integers. I'm not sure but you seem to use them to index arrays. But you've made them fixed point floats. In Rozmywanie (...).vi, you're even adding fixedpoint 0 or 1 to 0 or 2 using a saturated add... Every pixedpoint has a gates footprint, and I'd assume it's higher then an U8 (or Boolean).

The resolution of the fixed points is huge. Doubles should work on FPGA too, or so I'm told. Not sure if it will help for the size, but it would be far less prone to errors.

You're using Saturated Add a lot, while a normal + would do ( to add 0-2 to 0-2).

Even if you get it to compile, I highly doubt there aren't any bugs.