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02-21-2020 10:13 AM
Hello all,
I would like to decimate the output of a 50 MHz 16-channel module (5751B) to something around 10 MHz. Ideally I would like to average 5 samples on each channel input and produce one sample for each output.
It looks like something the "Rational resample" VI would be perfect for, but I can set it up for such high frequencies.
I was considering manually doing it by averaging samples in a SCTL and outputing only every other 5 iteration but I can't think of a way to code this properly. Any suggestions?
I am using LabVIEW 2016 on a 7972R target.
Thanks in advance!
Solved! Go to Solution.
02-21-2020 12:33 PM
I would use the functions in C:\Program Files (x86)\National Instruments\LabVIEW 2018\instr.lib\_niInstr\DSP\v1\FPGA\Public\Sub VIs\HB Decimator
02-22-2020 09:24 AM
If you wanted to do it yourself, I suspect given the FPGA limitations you'd probably want to do something along the lines of:
I suspect you can store a 16 element array in your shift register and add all the values at once. If not (I haven't used 2016 FPGA, but I'd hope this would work) then you might need to index the 16 elements, and have 16 separate shift registers, and duplicate the code 16 times.
You may also need to write to something like VI-defined block memory and have a While loop output to the FIFO (or setup handshaking and pipelines?) since you can't write 16 values to a FIFO inside a SCTL and doing this every 5 cycles, you can't even use the same loop I guess (maybe you already have channel-specific FIFOs?). In any case, perhaps you've already handled this issue?
02-24-2020 08:06 AM
Thank you both for your replies.
cbutcher, that's exactly what I was looking for. Your message made it clear in my mind, and I think it will work fine. I was unsure about how to output the sum only every 5 iterations, but I just realized that I can wire the "input valid" of the FIFO write to make it work. I haven't tested it yet but at least it compiles for my target, with the 16 element array as a whole in the shift register.
I will post updates when I can confirm that it works as planned.
10-07-2022 07:51 AM
Hi,
were you able to compile your code? i am going through the same issue and was hoping i can find a different way instead of using the built in "rational resampler" FPGA VI. however, it is impossible to control the decimator value. Could you send some example code or some guidance?
thanks!
10-07-2022 09:09 AM
Hi Villanul,
Unfortunately I have changed jobs since I started this thread and don't have access to the code anymore, nor do I have access to labview FPGA. My memory of this issue is a bit foggy but as I said in my previous post I was able to compile my code following the advice from "cbutcher". The idea is to have one shift register passing the sum being built over n cycles, and another shift register passing a counter being reset after n cycles. When the counter = n, you reset it and transfer the data with FIFO write wiring the "valid input" terminal (see Write (FIFO Method) - NI), and then also resetting the data shift register.
I hope this helps.
10-11-2022 06:40 AM
An alternative option is a Xilinx IPCore, CIC filter, which offers a "decimate" function.
10-11-2022 06:46 AM
HEy, thanks for the response. i was able to implement exactly what you mentioned in the thread and worked perfectly. I placed the decimate out function in a SCTL, and now i just need to re adjust the dt of the output waveform and divide by the decimation factor.
thanks again!