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FPGA->RT dma fifo Overflow and timeouts

Hi all,

 

i have FPGA that fills a DMA FIFO target scoped  @ 1 Mhz

On the RT host i want to process these data in chunks to avoid FIFO overwriting.

 

I can set the number of elements to read in one shot on the RT host side so i can read for example 10000 values in every loop so loop rate on RT side drops from 1Mhz to 100Hz in theory.

 

The problem is that processing these 10000 points takes longer than 10ms allowed.

 

Is there a way to process these 10000 values in another loop on RT host to not affect the FPGA->RT HOST data transfer?

For my task i don't care if i process chunks at slower rate but i have to ensure that all points are contiguous so what i've thought is to constantly flushing DMA FIFO on RT host and processing these data elsewhere.

 

Can you help me on this?

Thanks in advance.

 

MR

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Yes, stick the data in a queue to another loop. What hardware are you using? I recently tried to get that rate on a cRIO and with my logging, tcp, and slow fpga reading in other loops, it hit the processor at 100%. So you will have to do some benchmarking to make sure you can get the rate you want.

 

Also, make sure you set the FIFO depth property on the host application to make sure it can hold the data you need. I kept getting timeouts even though my DMA FIFO was set to a big enough size at this was why. 

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