FPGA fixed size array not resolved

[Thomas444]

I have problems recreating this example: https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/filtering-fpga-io-using-multiple-input...

I do totally the same as in the example - I have a fixed-size (sub) array [3] on the left (whats the thing with (sub)?), first shift register is okay (it produces fixed-size array [3]), array gets indexed to elements and back, and on the right, there is a variable size array. The right shift register throws error on build.

Even the build array with THREE elements does not produce fixed size array, so I don't get how the attached example could even work.

[Thomas444]

I have noticed that the build array thing behaves differently in top vi and sub vi - in top VI, it produces fixed size arrays. I tried to change reentrancy, input data type, size,  can't force it to work properly in subvi.

[Thomas444 · Accepted solution]

Solved this myself guys! 😄 VI Properties > Execution > Preallocate arrays did that for me. Weird, because labview preallocates everything on FPGA right?