FPGA execution time

[BeñatA]

Hi,

We are working in a HiL device and we want to speed up the execution time of the model. To do that, we have started taking just the most important parts of the model, which are the I/O and the clock calculation. We have seen that the execution time of the while loop is of 6.7 us. Is there a way to read write the modules in a faster way or we won't be able to speed up more the model?

We have a cRIO 9039 with a 40 MHz clock and the modules are 2x NI9401 and a NI9263.

Thanks a lot,

Beñat

[Andrey_Dmitriev]

You should use Timed Loop with 40 MHz source, then you will see that it iterates at 40 MHz:

Instead of per iteration time measurement you can add continuously incremented counter to that loop:

And then check how many increments you have within one second:

I have exactly 40 Millions cycles per second here.

[GerdW]

Hi Benata,

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@BeñatA wrote:

Is there a way to read write the modules in a faster way or we won't be able to speed up more the model?

We have a cRIO 9039 with a 40 MHz clock and the modules are 2x NI9401 and a NI9263.

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• You can read/write the DIO and the AO in parallel with two IO nodes.
• Some DIO modules allow reading/writing whole ports at once using integer values: I used that a lot with NI9403 modules…

[ZYOng]

I believe NI-9263 is the limiting factor here.

According NI-9263 Specifications

[Andrey_Dmitriev]

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@ZYOng wrote:

I believe NI-9263 is the limiting factor here.

According NI-9263 Specifications

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I don't think that the inserted module will affect cycle time, at least in my case I have also "slow" modules, like 9472 which is 100µs, but the Timed Loop still working at 40 MHz, also when I read inputs or write outputs. If inserted Module is not fast enough I just will get same not updated values during multiple cycles, but execution speed is not affected. But may be I'm wrong, I have no experience with 9263.

[GerdW]

Hi Andrey,

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@Andrey_Dmitriev wrote:
I don't think that the inserted module will affect cycle time, at least in my case I have also "slow" modules, like 9472 which is 100µs, but the Timed Loop still working at 40 MHz, also when I read inputs or write outputs. If inserted Module is not fast enough I just will get same not updated values during multiple cycles, but execution speed is not affected. But may be I'm wrong, I have no experience with 9263.

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In my experience I got compilation errors when trying to handle slow IO nodes inside fast timed loops (aka SCTLs).

That's why I put those IO nodes into plain while loops and added a wait function inside the loop to set the sample rate…

[Intaris]

Some modules have nodes which require them to be in either normal while loops or explicitly in SCTLs. This is defined int he CLIP.

The speed of execution of your code and the speed with which the IO is updated are not neccessarily the same thing. One could theoretically have a loop generating data at 40MHz, but if your IO is limited to 100kHz, I would question the benefit of such a design.

[Andrey_Dmitriev]

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@Intaris wrote:

Some modules have nodes which require them to be in either normal while loops or explicitly in SCTLs. This is defined int he CLIP.

The speed of execution of your code and the speed with which the IO is updated are not neccessarily the same thing. One could theoretically have a loop generating data at 40MHz, but if your IO is limited to 100kHz, I would question the benefit of such a design.

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In my particular case if was necessary to generate precision pulse trains from 9401 with different frequencies and delays for high speed cams and xray sync, also reacting on inputs, and I just let run RT Loop running at 40 MHz, then just implemented simple trivial counter, so, in easiest words, if I keep output true for 1600 cycles, then drop low to next 1600 cycles, then get 12,5 kHz output. It was so easy and works like a charm, fully meet my requirements.