Just sorted out some old FPGA compile errors, running into new ones today:
report_timing: Time (s): cpu = 00:00:49 ; elapsed = 00:00:13 . Memory (MB): peak = 8315.203 ; gain = 0.000 ; free physical = 3342 ; free virtual = 28719
# write_checkpoint -force "workerCheckpoints/route_design.dcp"
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:01:10 ; elapsed = 00:00:23 . Memory (MB): peak = 8323.207 ; gain = 0.000 ; free physical = 1640 ; free virtual = 28472
::ERROR: [Common 17-141] Failed to write file content of MacallanTop.xn in zip archive.
while executing
"write_checkpoint -force "workerCheckpoints/route_design.dcp""
(file "/opt/apps/NIFPGA/jobs2/T187W25_FBlMo2o/route.tcl" line 523)
invoked from within
"source "/opt/apps/NIFPGA/jobs2/T187W25_FBlMo2o/route.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 15:56:41 2024...
It seems that late in the compilation, the server has some problems writing to a zip file? I don't see how this can be dependent on my design, it would appear at first glance to be a server configuration issue.....
These compile server issues are happening quite often.... I will talk to my boss about setting up a local compile machine.
