FPGA compile failure

[MJ]

I've recently begun having frequent issues with FPGA compilation failures due to errors when transferring results at the end of the compilation.

I'm trying to compile code for a cRIO9102 using LabVIEW 8.2 FPGA.  The compilation takes 1 hour to complete and will use 99% of the available slices.  It had succeeded in a few occations after repeated trials.  But it fails frequently in my recent tries to transfer results at the end of the hour after generating a bitfile.  The final bitfile is not copied to the designated folder and I cannot proceed to compile the RT program for cRIO9012.

I hope someone can give me some hint how to resolve this issue.

Thanks.

Min.

[MattP]

Hello,

I'd like to help you get your FPGA app running smoothly, but to do so I could use some clarification.  First of all, do you have the compile server running on your machine or on a remote machine?  I'd like to make sure that networking issues aren't hurting you here.  To the same end, the compile server transfers its files over TCP/IP and can be subject to blockage by firewall packages, so you should make sure that the firewall is either disabled or set to allow this application to communicate. 

Normally at the end of the compilation process a report can be seen on the screen with the compile results.  The Compile Server status window should say "bitstream generation complete" - does it reach this step for you?  Do you disconnect from the compile server during the process?  If so, have you tried reconnecting to the compile by pressing the Run button on the top-level VI?

[MJ]

Hi Matt,

Thanks for your reply.  The compile server was running on my machine when the problem occurred.  The Compile Server status window did reach "bitstream generation complete" before it failed to transfer the results back to the compile client.  The final bitstream file was not generated.

After failing for a few times at the same place, I decided to disconnect the target (cRIO-9002 and cRIO-9102) from my host PC.  Then the compilation succeeded without making any change to my firewall, anti-virus settings, or my file searching programs.  Of course, I had to reconnect my target before downloading my new FPGA program.

I am happy to have a work-around to my problem but I have no idea why connecting to a target would cause FPGA compilation failure.

Regards,

Min.