FPGA compile error

[Mellobuck]

Good Afternoon,

I am getting a compile server error that I do not know how to track down. The server is set up and working fine (LV 8.6 cRIO, FPGA) I can send over on FPGA file and it compiles fine. When the second is sent, the compile request is received and starts, but a quickly get the following pop-up:

 

"Status: Compilation failed due to a Compile Server error.

Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation

Start Time: 2/17/2009 10:22:28 PM
End Time: 2/17/2009 10:22:54 PM"

I am aware that something is amiss in my FPGA VI, but I am unsure what the above messages are telling me to look at. Any ideas? It was working/compiling, but I changed the cRIO backplane configuration, removing some inputs and adding different ones.

Message Edited by Mellobuck on 02-17-2009 09:51 AM

[AdnanZ · Accepted solution]

Xilinx doesn't support a depth of 1. If possible carry on using a depth of 8 or use some other "register" to hold the value such as locals, globals, fifos, feedback nodes, etc. Have a look at the following:

Why Won't FPGA Code with a Memory Depth of 1 Compile?

[Mellobuck]

Brilliant!! I was using a memory space with depth '1' as a boolean global value. I will change that.