FPGA compilation problem

[JohnGrove]

Same here, I have a CAN message filter on an sbRIO-9632 FPGA that worked fine under 2010, but now fails to compile with a Xilinx duplicate object error in 2011.

NI support are looking at this, but I have reverted to 2010 in the meantime.

John.

[JohnGrove]

Turned out that my compilation problem was caused by a case structure with an empty default case (which was intentional, and compiled fine in 2010).

The fix for me was to right click the case structure, remove all empty cases, and then add a new empty default case.

No idea why this action should make a difference, but after performing it, the code compiled fine in 2011.

Cheers,

John.

[DavidMR]

Thanks for posting this John.

Removing 4 empty cases then adding them again fixed it for me too.

I was getting

'LabVIEW FPGA:  The compilation failed due to timing violations.', Non-diagram component, a CAN module. The cases were in 4 loops receiving CAN messages.

Last update was 1/2011 by somebody else so that must have been LV 2010.

At least it builds now. Onwards to the next problem...

David

CompactRIO 9022

LabView 2011 Professional, Version 11.0 (32bit).

[Daklu]

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@JohnGrove wrote:

Turned out that my compilation problem was caused by a case structure with an empty default case (which was intentional, and compiled fine in 2010).

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Thanks for the tip.  I was running into the same error message as the original poster after copying a block diagram from one project to another on the same pc.  It had one case structure with an "empty" case (connected wire terminals but no functions.)  Deleting and recreating the case worked for me too.

LV2012 f1 (32-bit)

cRIO-9074

Xilinx 13.4 (64-bit)

[Daklu]

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@Daklu wrote:

Deleting and recreating the case worked for me too.

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I take it back.  It compiled once but further edits have caused the error to resurface and I can't get rid of it again.

[Stu_E]

Hi all, 

I just ran into this same problem and wanted to add that this fix worked for me too.  I'm on a real-tight timeframe, so trying a new version of LV FPGA would be my last resort, so I'm very thankful for this post.  Thanks!  

My design compiled fine in LV FPGA 2011 SP1 (Xilinx 12.4) and had been running fine, I ended up changing the default case in a case structure (as well as a FIFO size) and then I got this compile error.  Fortunately I found this post and in my case I was able to remove the case structure and use a few select vi's and it recompiled and ran fine.

Many thanks!

Stu

[vgravel]

Same problem here...

Everything was compiling fine but now, I run into the error.

The final Timing seems OK to me (see the picture attached). Also, the error seems to appear at the very end of the compilation. The last entry in the Xilinx Log is "Process "Generate Programming File" completed successfully" (see the picture attached).

I would like to have someone from NI thoughts about this.

[fromm8]

Hi vgravel

Could you share more information about your set up so we could research more about it? RIO version, LabVIEW FPGA version, Xilinx tools version?

Was it compiling fine before? What changes did you make before get this error? Could you attach the xilinx log to the thread?

A recommendation: it is always better to start a new thread in these cases because this one is old, and if you use an appropriate title more people with knowledge on this could get involved (and we can keep order).

Regards

Frank R.

[tommpogg]

I have exactly the same problem. The compilation fails due to timing violations, but no path information is provided.

Moreover, the Xilinx log reports that the compilation has been successfull.

These are my systems settings:

LabVIEW FPGA 2012

FPGA board: NI PXIe-5641R

Xilinx tools version:13.4

Regards

[fromm8]

Hello tommpogg

Your xilinx tools is the correct for LabVIEW FPGA 2012. About the error, that could due to: Timing Violations When Using DMA FIFOs Wider than the Datatype Pushed Through.

You could read this document and take into account the recommendations at the end of the document (links under references). High Data Rate Filtering on the NI PXIe-5641R RIO IF Transceiver.

Again, each issue is different and I recommend you to start a different thread so we can analyze each case individually and help you better. We should keep order with the documentation.

Regards

Frank R.