FPGA clock generation

[codeman0624]

Is there a way to generate two FPGA clocks with a known phase difference?  I'm using a 7954r, which is a Virtex 5.  I know there are internal DCM modules that generate clocks with phase shifts.  I've tried adding a CLIP that's just a DCM within the FPGA, and Labview accepts it, but I don't know how to then take these new clock outputs and make Labview know that they are FPGA clocks that can be used.

How can I do this?

[smithd]

Hey codeman,

I just confirmed that we can do this, and it is actually fairly straight forward.

First, save this vhdl file as ClipGenerateClk.vhd:

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahelp/fpga_clip_clock_ex_code/

Then import it into labview fpga as CLIP, and be sure to specify that the clock outputs and inputs are of the clock type:

After you have done so, you should have a fully functioning pair of 80 MHz clocks which are offset by 180 degrees.

Let me know if you have any further issues with this.

Thanks,

[冬旭]

How to use the DCM management IO module clock In FlexRIO ?

[REDS]

Hello,

Can you be a little more specific? I don't understand your question. Is there something from the posts above that you want us to clarify?