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FPGA case structure

hi,

 

  i'm developping a simple LV FPGA program on a compact rio using the 9401 module.

 

  i'm tryning to controle sequencely the DIO of the module by a flat sequence (sequence -> delay-> sequence->delay) , (see picture attached), i'm not sure it will work, 

 

  what i your opinion on this side?

 

  Regards,

SASA

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Message 1 of 13
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Hi SASA,

 

use a flat sequence instead of a stacked one. Until now we cannot see, what's happening in those other 2 frames…

 

- You only open the FPGA VI ref once, so closing it twice seems not right to me…

- As your while loop never stops you will never close your FPGA VI ref…

 

Hint: Did you notice this little "Auto Cleanup" button in the menu? Guess what it's for…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 2 of 13
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You have to configure the DIO direction (Input/Output) first before accessing the IOs. By default your DIOs will be in the Input mode and you have to Enable the Output before accessing it as DO.

-----

The best solution is the one you find it by yourself
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Message 3 of 13
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Hi GerdW,

 

  😉 i always used "auto cleanup" button, 

 

  at the begining  i tried the solution you described, but stacked sequence seems to me less consuming in the vi space 🙂

 

 but i will re-use it,

   

 olz see the picture attached,

 

Regards,

 

SASA

 

   

 

 

Hi SASA, use a flat sequence instead of a stacked one. Until now we cannot see, what's happening in those other 2 frames… - You only open the FPGA VI ref once, so closing it twice seems not right to me… - As your while loop never stops you will never close your FPGA VI ref… Hint: Did you notice this little "Auto Cleanup" button in the menu? Guess what it's for… Best regards, GerdW CLAD, using 2009SP1 + LV2011SP1 (sometimes even LV2014) on WinXP+Win7+cRIO Kudos are welcome Smiley Wink

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Message 4 of 13
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Hi SASA,

 

between execution of the last and the first frame (when the loop spins) there is no delay. So right after setting/reading DIOs they will be read/set again.

I don't think that's what you want…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 5 of 13
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Hi GerdW,

 

   didi you have seen the waiting "ben" of 200 ms, it's a waiting time, didi you think the opposit?

 

  Regards,

 

SASA

 

 

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Message 6 of 13
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Hi SASA,

 

yes I have seen the wait instruction between frame 0 and frame 2. But what's the wait time between frame 2 and frame 0?

 

When frame 2 is finished the loop iterates and frame 0 is executed instantly - resetting all DIOs so you will NOT notice any changes on the output pins…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 7 of 13
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HI GerdW,

 

  so what solution you have in mind (delate the while loop)?

 

  Regards,

 

SASA

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Message 8 of 13
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Hi SASA,

 

you need a wait function after frame 2…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Message 9 of 13
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Hi GerdW,

 

   I will come to you after testing the code.

 

  Thank you very much.

 

 SASA

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Message 10 of 13
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