FPGA array

[lightmiddle]

I am using PXI 7833R which has 3M gate reconfigurable I/O (RIO) FPGA with 190 kB of embedded RAM.

Now I want to build an array with 3000000 elements, is that possible?

My test pattern is in form of .txt file, how can I send this data to the FPGA array through the Host? It seems that I can not write an array control from the Host to the FPGA through the "Write and Read Function" . Is there any good way to do this?

Thanks

[Christian_L]

Using the 3M gate FPGA you can not store an array with 3,000,000 elements. The best option is to use the 192 kB of memory but that will not be enough for what you describe.

If you try to implement an array in LV FPGA which will be implemented on the FPGA, you will only be able to allocate a few hundred elements, because implementing data storage on the FPGA is very inefficient.

In general you can implement small arrays on the front panel of the FPGA VI and read or write them using the Read/Write node from the host VI.

Depending on how fast you need to output your test pattern, you may be able to store the data in the host VI and stream it to the FPGA as it is being generated. You can use the 192 kB of memory on the FPGA to buffer the data between stream from the host and outputing from the FPGA.

Can you provide more details about your applications? How fast do you need to generate the data? Digital or analog? Will this buffer be generated once or be repeated? Is your host application running in Windows or LabVIEW Real-Time?

[lightmiddle]

Hi Christian:

My application is to use the test pattern (stream of data) to generate a digital (output) signal  and get a digital (input) response from the tested device . My host is Labview windows. The test pattern includes at least 200000 element.

My plan is to through Host VI stream the pattern into an ARRAY in the FPGA VI, then do a comparison between the digital in and expected pattern in FPGA VI. The better way is to stream the pattern in and store the pattern in an Array and then I will not use the Host. What else will be done inside FPGA.

I hope the test can be runned at 8M Hz. However when I used the array to generate a digital signal, the frequency was around 1.6MHz. And then I tried the  Timed loop, I could get a 20MHz signal.

The problem now is that what I can get is 20MHz or 1.6MHz below , I could not get a frequency between 20 and 1.6 MHz.

By the way if I wanna use the memory, how can I do it?

Any suggestion?

Thanks again.