FPGA - Simulation (Real I/O)?

[UnholyPenguin]

I'm confused about the purpose of Simulation (Real I/O).  It seems I still need to synthesize a bitfile before running in this mode.  What is the purpose of this mode?

[ZYOng]

From Testing and Debugging LabVIEW FPGA Code

Simulation (Real I/O)
In this mode, real data is acquired from the inputs of the FPGA target, passed to the host computer, and consumed in the simulation environment. Changing FPGA output values in simulation results in the physical changes to the FPGA hardware output. This execution mode is reserved for R Series targets only.

You need to compile a minimum bitfile to interface with the inputs. I believe that the compilation time is way less than the full bitfile.

[UnholyPenguin]

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You need to compile a minimum bitfile to interface with the inputs. I believe that the compilation time is way less than the full bitfile.

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That would be fantastic, I'll try to confirm that.  Thanks.