FPGA Sampling Rate Issue w/ 9205 Module

[mecksone]

I’ve been having some sampling rate issues using the 9205 AI module on a cRIO-9081. I'm using an Omega linear variable displacement transducer and I want to collect the AI data from the +signal. The goal is to get 10k samples per second out of a single channel of the module, however I’m barely getting over 1kHz. I’ve developed some Vis in FPGA which are modifications of the examples provided in LabVIEW to suit my needs. Basically, I need the AI data and the elapsed time it corresponds to. I’ve setup an elapsed time and express table VI to handle this. I’m wondering if this could be the issue behind the sampling errors as maybe the table cannot compile fast enough. I’m open to all suggestions and ideas. Thanks in advance.

Andre B.

*I will post images asap. The page won't allow me to upload them. I can also have the VIs converted if needed.

[Zach J]

Hi mecksone,

Typically with FPGA programming, it is best to have the FPGA perform the absolute minimum of functionality to get data somewhere it can be processed more efficiently.  In the case of a cRIO, this would be to acquire the data and then use a DMA FIFO to pass the data to the real-time controller.  The real-time controller could perform the rest of the necessary analysis on the data.  It might be very helpful if you could produce a screenshot of your code.  I think we may be able to help provide some suggestions on doing this if we can see how things are being done currently.  

[GregFreeman]

Yes an image would be helpful, and the code would be more helpful. Images will upload...just save them as .png files (don't just change the file extention, but actually open them and save as png).

I have used the 9205 before so I should be able to help.

[mecksone]

Here are screen shots of the FPGA and host VIs. Thanks for the help. I've only done some basic work in LabVIEW, specifically in scan interface, so I will have to look more into DMA and other specifics with FPGA programming.

[mecksone]

Here are the VIs done in LabVIEW 2012. Thanks again Zach and Greg!

[GregFreeman · Accepted solution]

The FPGA is reading at the rate you want. The problem is you are reading that control value on the RT, so the data you get is limited by the RT loop time.

So, the FPGA could be reading a values at10,000 hz, but they aren't being buffered. If the RT is only running at 1,000 hz, you will read every 10th data point. You need buffering as Zach mentioned. Look for examples in the LabVIEW help using DMA FIFOs for buffered acquisition. That is what you need here. You would buffer data, then read it in chunks at a slower rate on the RT.

[mecksone]

Thank you both for the help. I guess the question now would be why am I not getting any values into my table? The table populates with 0s where displacement should be. I've been researching DMA FIFO specifics and I have a better idea of it, but still far from an expert. After playing around with it my concerns are how to modify timeout, number of elements, and loop time in both FPGA and host to get the 10kHz I need. I've still got some more research to do but any guide in direction is greatly appreciated. I've attached screen shots of the VIs.

FIFO:

-Target to Host DMA

-1023 Number of Elements

-I16 Data type

[mecksone]

The VIs

[GregFreeman]

Set your FPGA loop time to be 10,000 hz. Set your RT loop to have a dt of 100 milliseconds. From the FIFO, read 1,000 elements at a time with a timeout of -1 on the FIFO. The timed loop is managing its acquisition rate so no need to worry about timeouts on the FIFO read for this example. All the data should be in the FIFO by the time the next read happens. Set a timeout of 0 on the FIFO Write. This setup corresponds to reading 1,000 elements from the FIFO every 100 ms, so you will read all 10,000 elements in 1 second.

You won't need to worry about timeouts here. It's usually a good idea to have your application be able to recover from timeouts, but take this one step at a time. Something this simple really doesn't need timeouts to be managed, because your FIFO should never overflow anyways if your code is set up right.

As for writing to your table, I think you are having issues because you are getting 1 timestamp but you have multiple points. You need to create an array of timestamps. So, since you are reading 1,000 samples at a time (remember, you are reading 1000 samples every 100 ms) you will need 1,000 timestamps, each one 0.001 seconds apart. Now, this array of timestamps and your data is what you want to use to build a table.

Also, as a note, there is a VI in the FPGA Interface part of the palette on RT that will convert sample rate to ticks/us/ms so you don't have to do the divide by 1,000,000. It will also take into account the clock rate on the FPGA

[mecksone]

The timing method makes sense and seems to work properly number wise. However, I'm still not getting any values from the AI0 channel besides 0.00000. I see what you're saying about the timestep and I will have to configure that at a later time, but the actual voltage from the channel does not get fed through. It's as if the array is not being converted properly. But again, thanks for all your help!