FPGA Runtime Version Register

[tkreider]

Is there a way to get a version number or compile timestamp of a LabVIEW FPGA bitstream from within the FPGA while running?  I would like to be able to have a build number embedded in the FPGA so when it's running it can report the compile version without resorting to manually populating a control, global, BRAM, etc.

Not being a heavy LabVIEW scripting user, does anyone know if a compile can be kicked off within a script?  This would let the script update the source with a version and then build it in one step.

What would be great is a VI in the the NI libraries that replies with a U32/U64 based on the compile time in seconds (like the time/date to seconds function in Windows).  Then no extra steps are needed to embed the data. 

Any ideas?

[Dave.C]

Hi tkreider,

If I'm understanding your question correctly, you could use the File I/O functions (Open/Create/Replace File, Read from Text File, Match Regular Expression) to parse the bitfile for the Bitfile version.

I'll continue looking into kicking off a compilation with a script.

[tkreider]

Thanks Dave.  While this solution works within LabVIEW for Windows, those features (Open/Create/etc) are not available within the LabVIEW FPGA target scope.  I tried making an initializer VI for a VI Scoped memory within LV FPGA which returns a timestamp (2 U32's with the initializers run-time in seconds using Time in Seconds).  Unfortunately, the initializer isn't called at compile time automatically, it must be run by hand before starting the top-level compile.

What I would like is a way to have that initializer run for me at top-level compilation time automatically.  If there is some way to read it from within LV FPGA without creating my own hack (memory) that would be great.  Say maybe, a block that reads a timestamp from the Xilinx bitstream in flash...  🙂

Thom

[Dave.C]

Hi Thom,

In consulting with colleagues, we haven't identified a way to do it on the FPGA.  It has to be determined from the host because that is where the bitfile resides (real-time, Windows, etc.).  The idea is to browse the bitfiles in a specified directory and look at the last updated time.  This will give you the time of when it was built or deployed (depending on OS).  Keep in mind that it will only work if it's set as the startup application on the real-time target.

[tkreider]

Dave,

Thanks for taking up the cause.  Let's supposed that the FPGA bitstream is deployed to the hardware target to start on power-up without a controller yet running.  The bitstream is parked in flash and without anything else running, I'd like to know the timestamp of the build that is running.

Thom

[Dave.C]

Hi Thom,

Still working on this...  The thought is to parse the bitfile and write the version to a register or memory on the FPGA.  FPGA does not support the timestamp data type.

Could you provide me some of the bigger picture?  Why do you want the timestamp or version number and how will you use it once you have it?  

[Dragis]

This sounds like a good feature request for the FPGA Idea Exchange. The Build Specifications already have the notion of a version, so one very simple request would be to include that version number in the compiled image of the device (it currently just resides in the LabVIEW FPGA bitfile, not in the image for the actual hardware). A step further would be a register with the actual compile time, but there you get into timezone and other issues.

[tkreider]

Dave,

I have an application where the FPGA has several communications links to the outside world.  Over those links, we would like to be able to query the FPGA as to the revision number of the running IP.  Having the FPGA report its revision number based on information given to it from another device (with a different revision number) isn't the most reliable mechanism.

Having something like a timestamp embedded in the FPGA that can be trusted would be ideal.  Having to update the register manually before compilation leaves the process open to a high-probability error on the operators part.  Having an external entity inform the FPGA as to the FPGA IP revision number is also ripe to several more failure modes.

It seems like this should be added to the FPGA feature request page as suggested.  While I have access from the FPGA at runtime to the raw bitstream file in Flash, staying inside the toolchain and having LV reporting the data would be ideal and applicable to the larger LV user community.

Thom

[Dave.C]

Hi Thom,

If you're not familiar with the FPGA Idea Exchange, you can click here.

[tkreider]

Dave,

So it sounds like we've run out of options on getting LV support for the version register within the existing tool?  I'll post to the Idea Exchange if we agree we exhausted our options.

Thanks for your help!

Thom