FPGA Reference broken wires

[tommpogg]

Hi,

I use a subVI to pass some parameters from the Host to the FPGA using the "Read/Write Control" function.

This subVI takes a "FPGA Reference In" as an input and provides an "FPGA Reference Out" as output.

The problem is that whenever I make some changes to the FPGA code (e.g. I change the type of one input/output), the wires entering the subVI are marked as broken since the FPGA reference has changed.

Now, I know that I can solve the problem by opening the subVI, right clicking the FPGA Reference and configuring it. But this must be done manually and I would like my subVI to automatically detect any change.

Is it possible to do it?

Thank you

[christian_w]

There are several options to handle this. I prefer to use a Global Variable to hold the FPGA reference and I activate the dynamic mode.

Hope it helps

Christian

[tommpogg]

Interesting, but I would like to avoid filling my code with many instaces of a global variable.

Isn't there another way?

[Dragis]

You can create a typedef and use that type for the controls/indicators of your subvis. You still have to manually configure the typedef, but at least you only have to do it in one place.

[nathand · Accepted solution]

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@Dragis wrote:

You can create a typedef and use that type for the controls/indicators of your subvis. You still have to manually configure the typedef, but at least you only have to do it in one place.

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You don't need to manually configure the type def.  You need to create the type def once, and replace all your existing references with it.  Then, on the block diagram, find the Open FPGA VI Reference function and right click to configure it.  At the bottom of that box, you'll see a "Bind to Type Definition" option.  Check it, and enter the path to the type definition you created.  Close the dialog box.  The type definition will now automatically update to reflect changes to the FPGA VI.  See http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgahosthelp/fpga_using_subvis_in_host_vis/ for more information, and if you're using LabVIEW 2009, follow the instructions from http://digital.ni.com/public.nsf/allkb/2906287B989006EA862576AB005BE08E

[Dragis]

In older versions of LabVIEW, the "Bind to Typedef" functionality was the way to go. However, that functionality is being deprecated because it doesn't give you the flexibility to make truly reusable VIs. The now standard dynamic mode for the FPGA Interface let's you restrict the interface seen by a VI to only what is necessary for that VI. This makes it much easier to share VIs between multiple builds of an FPGA application. However, it does mean that you may have multiple typedefs (with the solutions mentioned) which are more generic than what you got with the "Bind to Typedef" in the past.