FPGA : Possibility to load an encrypted VHDL file

[CyGa]

Hi,

For a new project we might need to load a VHDL IP into our LV FPGA development.

The IP's provider says that the VHDL files are encrypted.

Is LV FPGA able to import such files ?

If needed, the provider can re-encrypt the files with a specific pragma code.

Would it help ? If yes, what would be this pragma code ?

[Jimmie_A. · Accepted solution]

Hi,

This is more of a Xilinx question than a LabVIEW FPGA question, since we use Xilinx compilers such as ISE or Vivado to perform the compilation.

As an end-user I believe you don't need to worry, if you would like to encrypt your own VHDL IP you would need a license from Xilinx whereas if you need to use encrypted VHDL from a provider you don't need a license. In what file format will you get the IP?

The Xilinx tool will manage how to interact with the encrypted IP.

If we look at Vivado for an example, it supports IEEE-1735-2014 Version 2 compliant encryption and covers HDL design entry up to the bitstream generation and the authors/providers of the IP can then manage how the tool can interact with their IP.

[CyGa]

Hi Jimmie,

Thank you for the update!

The IP is provided as a set of VHDL files. But it seems that they made their own licensing system, because they do not use the Vivado encryption solution. We've got some troubles loading the IP, but it is pointing on their own-made  protection solution.

We'll try to fix this on our end.

Thank you for the support !