FPGA Parallel

[bahec666]

Hello,

I'm using NI PXIe-7966R FlexRIO and i want to create FPGA application.

I have three SCTL. Two of this loops are in the same clock domain.

When i'm compiling this loops one by one there is no problem. But when i'm compiling this loops together there is timing error occures. I thought, that they will work in parallel, but this is not true. How i can run this loops in parallel?

And in one of this loops i have 20 random numbers(Amp1, Amp11, Amp2, Amp12 etc. see on picture 1). If pulseNumber in FIFO is 20, i want to sum this 20 random numers. If pulseNumber is 15, for example, i want to sum only 15 random numbers. If pulseNumber is 0, there is 0 in the output. Compiler writes to me, that this loop is the longest. How i can realise this algorithm in 100 MHz SCTL?

[scotia673]

Could you post a screenshot of the timing violation information you see when you compile them together? In any case, it's more than likely just a matter of trying to do too much at once. Take a look at the link below for information on how to optimize your FPGA code to reduce the likelihood of running into timing violation compiletime errors. 

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_fix_timing_violations/

[natasftw]

When you compile successfully, what percentage of your resources do all three of the loops say they take?

You posted pieces of your code.  Do you have any shared resouces with those loops?  Any FIFOs more than one draws from or anything of that nature?