FPGA - Multirecord Acquisition for 4 Channels

[Arbores]

Greetings all,

So, in this https://www.ni.com/en/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumen... link on Figure 4. 

These two VIs - 1. Select and Interleave and 2. Write VI can be used for at least two channels or just one channel if I treat it as one channel to get the trigger level for A and B (Or trigger). 

My question is, how can I add multiple Or triggers for four channels and pass it to the 1. Select and Interleave and 2. Write VI with trigger status and timestamps? Right now I see two wires that goes to the feedback node to the 1. Select and Interleave and 2. Write VI. 

Do I need to combine four Trigger.vi and see which one got trigger and pass to the Select and Interleave and Write VI? 

Thanks,

Arbores

[Terry_ALE]

This example can be changed to do many things.  What do you need?  Some questions:

1. How many channels will see a trigger?

2. Are you looking for triggers on more than one channel at the same time?

3. When a trigger occurs which data do you need to save?

[Arbores]

This example can be changed to do many things.  What do you need?  Some questions:

1. How many channels will see a trigger?

all the channels 

2. Are you looking for triggers on more than one channel at the same time?

Yes

3. When a trigger occurs which data do you need to save

I would like to save pre-trigger and additional number of samples after the trigger. For example save if pre-trigger is 200 samples and number of samples is 1000 then save ==> 1000 samples that includes the pre-trigger and the number of samples.

Thank you!

[Terry_ALE]

From LabVIEW go to

File >> Create Project

Select Oscilloscopes

There are 2-3 project examples that I recommend you run and try out.  This can help you see what can be done out of the box and then what next steps would be.

[Arbores]

Hello @Terry_ALE,

I saw those projects and those projects are similar to each other. Non of them implements 4 channels but instead always one channel that can have A and B trigger level (or can be used as two channels) which doesn't really help me implement 4 channels that has A and B trigger level per channel. 

Thanks!

[Terry_ALE]

Yes, there is similarity between the projects.  FPGA VI is the same for all.  Host is different.

This can be modified to support what you mentioned above.  First step is to understand this code.

[Arbores]

Hello @Terry_ALE,

I think I do understand what is going on. The figure below shows what I am trying to do (This will not work, I know). There is an option that I can see which it is to only pass whichever channel got trigger but what if one gets trigger just after one got trigger? I lose data there.

Multiple channels Interleave and Write.vi

Thanks!

[Terry_ALE]

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@Arbores wrote:

Hello @Terry_ALE,

I think I do understand what is going on. The figure below shows what I am trying to do (This will not work, I know). There is an option that I can see which it is to only pass whichever channel got trigger but what if one gets trigger just after one got trigger? I lose data there.

Multiple channels Interleave and Write.vi

Thanks!

---

When you make a copy of the Multi-Record Acquisition (function circled to the right), it needs its own reference and code outside of the loop that 'instantiate' it.

In the code at the top of the diagram, you will need one set of trigger logic for each channel.  Four copies.

[Arbores]

I don’t understand what you are saying completely.

So, same while loops 4 times but for each channel?

[Terry_ALE]

The current FPGA VI has a loop that you are showing.  To the left of this loop is the following code:

It has functions such as the Create Resources.vi which setup the Multi-Record Acq for use in the loop.

If you make more than one Multi-Record Acq (as in your screenshot) you need another one of these.