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FPGA Making 2 loops start simultaneously

Hi,

I have an FPGA vi which contains multiple loops and i would like 2 of the looops to always start simultaneously always

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Mensagem 1 de 6
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Hi nowoxi,

 

THINK DATAFLOW!

 

With correct dataflow the loops will start at the same time...

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Mensagem 2 de 6
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Hi,

I pass data to the 2 loops by FIFOs and they are written in parralelt so i believe they should get data at the same time. is there a reason why 2 FIFOs in parrallel with everythign identical except the names ofcos will not transfer data at the same time?

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Mensagem 3 de 6
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Hello, 

If you would like more information on parallel execution in FPGA then I would suggest you take a look at this link that gives you detailed information about it and also shows an example for doing the same. It will also give you some information about pipelining.

 

Optimising your LabVIEW FPGA VIs: Parallel Execution and Pipelining -  https://www.ni.com/en/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumen...

 

Another useful resource for you would be the Getting started with LabVIEW FPGA, this webpage has videos/tutorials which can help you with you programming . Please click on the link below to access this page :

 

https://learn.ni.com/learn/article/getting-started-with-fpga

 

Also if you search 'Using Graphical Loop Structures in LabVIEW FPGA' there is a great video in there by National Instruments that can help. I would have posted the link here but the page restricts me from doing so. 

 

Hope this has helped you.

All the best with you Application 

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Thank you Shruti,

I would use the inofmration you provided I am grateful. Do you have an idea why my VIs dont act the same way everytime. Atimes I run it and all the components run, other times they dont.

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Mensagem 5 de 6
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You are welcome! This could be a problem with the code..if you like you can upload your code and I can have a look to see where the problem may lie?

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