FPGA Initialization code

[Benvalet]

I am writing an FPGA code that will just perform an intialization process (bring Analog Ouput values to ZERO).

Once the SET/RESET button has been pressed, the Analog Output should always  give aZERO even if the button is released.

I am using LabVIEW 2011.

The HOST and FPGA VIs are as attached.

[A.E.M]

... and what's your question?

By the way: There is no point in having the outer loop in the FPGA, as the inner loop will never stop.

And always remeber to add a delay on windows. Use the "Wait (ms)" function - even a 1ms delay will mean a lot to Windows 🙂

[Benvalet]

Thanks for your response AEP.

I am sorry my question was not clear.

I want the code to do an initialization process.

Right now, in the TRUE state, SET/RESET BUTTON returns a zero value whereas in the FALSE state, the input value is given as an output.

The code should return a zero value once the SET/RESET button has been pressed and remain zero even in FALSE state.

How can I make this possible? Any clues or suggestions will be highly appreciated.

Kind Regards,

Opuk

[crossrulz]

In your Host VI, use an event structure so that you only send data to the FPGA when you change the Input Value or press the reset button.  In the Reset's event case, use a local variable to set your Input Value to 0.

[Benvalet]

Hi Crossrulz,

Thans for your response. I have tried to implement your suggestions but it seems I still dont get the proper output as expected.

1. The input value is not reflected as the output digital values in HOST VI.

2. The output is always the current value in the FPGA VI output (in this case 0) and not the digital values calculated from the HOST.

3. In the Reset event's case, TRUE and FALSE state still gives different  outputs. The output should be 0 in both TRUE/FALSE state.

Any further clues? Attached are the updated HOST and FPGA VIs

Best Regards,

Ben

[crossrulz · Accepted solution]

1. The Input Value in your FPGA needs to be INSIDE of the loop.  Otherwise it is just being read once.

2. Rename your "Set/Reset" to just be "Reset".  It makes it a lot more clear what it does.

3. In your FPGA VI, make the Reset button a latch type for the mechanical action.  This will force the value to go back to False all on its own after the Reset was read.

4. Some cleaning up of th event structure code needed.

See attached to see how I set it all up.

[Benvalet · Accepted solution]

Hi Crossrulz,

Thank you so so much for your last response. Actually, you just solved my problem. You take all the credits and I appreciate.

I have been working on this for more than two weeks but in vain.

But just for my ignorance, what role does panel close case play? And why must it come in between Input value change case and reset case?

Thanks for your immediate response. Stay blessed.

Best Regards,

Opuk

Kudos

[Benvalet]

Hi,

I included a move feature in my code, but the behaviour is kinda funny.

When I give a new value to the FInal destination (control) the value changes but I want the change to take place at the desired move speed which is not the case. The changes take place spontaneously.

Then, when the HOST VI is run, all my indicators does not show any values as expected. What could be the problem?

Any clues or suggestions will be highly appreciated.  Attached are my VIs.

Best Regards,

Opuk