FPGA Indicators

[Schrodinger1933]

Hello all

I know in order to optimize the speed the FPGA can run, I need to limit the amount of indicators on the FPGA front panel and use DMA FIFOs where appropriate. Where I'm confused is I am unsure at what data size it is more efficient to use a DMA FIFO. I have 13 indicators in my FPGA code, and am not sure what data transfer mechanism to use. Thanks.

[lagelian · Accepted solution]

There are two main methods to transfer data from your FPGA to RT target - front panel controls/indicators and DMA FIFOs. DMA FIFOs are going to be the fastest method if you are transferring large amounts of data between FPGA and RT, while front panel control/indicators will be dependent on the speed and availability of the host processor and are better for small/infrequent data transfers.

For more information on these two methods, I would consult the cRIO Developer's Guide (starting on page 89).

https://www.ni.com/en/forms/compactrio-developers-guide-full.html

Additionally, here is a help document for optimizing FPGA VI speed.

https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/optimizing-fpga-vis-for-speed-and-size...