08-28-2017 12:03 PM
Hello all
I know in order to optimize the speed the FPGA can run, I need to limit the amount of indicators on the FPGA front panel and use DMA FIFOs where appropriate. Where I'm confused is I am unsure at what data size it is more efficient to use a DMA FIFO. I have 13 indicators in my FPGA code, and am not sure what data transfer mechanism to use. Thanks.
Solved! Go to Solution.
08-29-2017 09:16 AM
There are two main methods to transfer data from your FPGA to RT target - front panel controls/indicators and DMA FIFOs. DMA FIFOs are going to be the fastest method if you are transferring large amounts of data between FPGA and RT, while front panel control/indicators will be dependent on the speed and availability of the host processor and are better for small/infrequent data transfers.
For more information on these two methods, I would consult the cRIO Developer's Guide (starting on page 89).
http://www.ni.com/pdf/products/us/fullcriodevguide.pdf
Additionally, here is a help document for optimizing FPGA VI speed.
http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgaconcepts/optimizing_fpga_vis/