FPGA FIFO and Memory R/W Speed

[henry_2020]

Hello,

What's the data transfer rate in FIFO (Type: Target Scoped, Implementation: Block Memory) or Memory (Implementation: Block Memory) ？

Card: PXI-7965R

Thanks

Henry

[MaxJoseph]

Are you asking whether it is better to transfer data around the FPGA using a target scoped FIFO or Memory?

I use memories when I need to look back in time, when I am implementing a pretrigger. I use target scoped FIFOs when I want to get across clock domains or when I want to implement clusters.

Basically, which one you use depends on what you need for your application. Can you give us more information about that?

[henry_2020]

Hello，

I acquire data in 160MSps, I need to rearrange the datas in FPGA.

So I want to know the speed that I write to and read from the target scoped FIFO/BRAM.

Thanks.

Henry

[MaxJoseph]

You can easily manage that data rate if you read a sample a cycle in a single cycle timed loop. The question is if you can rearrange the data in the time that the loop has to operate (only 6.25 ns!). If not then you will need to read two samples at a time etc.

What kind of rearrangement do you need to do?

Where does the data come from? Can you send it to the FPGA at 160 MSps?

[henry_2020]

Hello，
I acquire 16 channels data at 10MHz，same as a1, b1, ..., p1; a2, b2, ...p2...
I want to send data to DMA in the following order, a1, a2 ...a10; b1, b2 ...b10;...p1, p2 ...p10...
In order to do so, I need to put the data into the BRAM or FIFO.
In my test the BRAM can run(R/W, U32) in a 140MHz SCTL, the target scoped FIFO can run in even in a 200MHz SCTL. So what parameters determine the SCTL timing soource rate, or the speed when R/W BRAM or target scoped FIFO?
Thanks.
Henry

[Intaris]

Yes, this should be do-able.

Instantiate a BRAM with double the depth you require, so for 16 channels, this will be 32 elements deep. Width depends on your datatype.

Define a Boolean "Page" which inverts every time your full 16 channels are read (so every 16 cycles inverts).

In your loop, write to Index 0..15. Use the "Page" as the MSB of your index (0..15 this cycle, 16..31 next cycle).

At the same time, read from the index you require for your DMA transfer (if you're lucky a bit of bit-twiddling may convert one index to the other but int he worst case, just use an array), but with the "Page" inverted. (16..31 this cycle, 0..15 next cycle). This will make sure you are transferring full blocks of 16 elements without inadvertent interleaving of packets.

You might think the BRAM is superfluous but it should work nicely and guarantees intact data blocks of 16.

Edit: I think you may need 320 elements (10 instances of each channel), but even this should be do-able.  You might need more work to make the index translation not too resource-hungry. Make sure to choose latency 2 or 3 for the BRAM. This should be able to extend well above the 160MHz you require.  BRAM with only one latency will be more limited.