FPGA FIFO Read issue, write & read count mismatch

[Orbel.Sevoyan]

Hello All,

I need some help with my FPGA code, I am writing 8000 points to FPGA and then just reading back, but on first call of "how many points are availible in FIFO" (Just reading 0 points and checking how many left) I am getting wrong value. Why on first call and second call I am getting different values?

Please check project and you will see what I am talking about.

Orbel

[AgentAstronaut]

Have you tried removing the shift register in the for loop? I'm not certain it will do anything.

[Orbel.Sevoyan]

Hello  AgentAstronaut,

Thank you for your reply.

First issue was found when we where using this same code without for loops (Which means without shift registers), I have placed for loop when we found that second run gives proper value.

[Dragis]

Glancing at the FPGA VI, I'm not sure how this will work the way you want it to. The FPGA VI seems to wait until the FPGA side sees all 8000 elements before reading but after the first read the elements available for reading drops to 7999 and no more reads will take place.

[speleato]

One other thing to add. The FIFO moves data asychronously. The ReadFifo and WriteFifo methods on the host move data in and out of the DMA buffer and signal to the hardware that data transfer is possible, but they don't actually, directly cause data to move between the FPGA and the Host.

That is to say, it makes perfect sense that the elements the Host DMA Buffer would change between calls, as the hardware is moving data in the background.

Sebastian

[Orbel.Sevoyan]

Hello Speleato,

Thanks for reply, but if you look at the code there is delay between write and read and it 2 seconds, which I think, is much more than enough to transfer 8000 samples. This issue is you should check twice to get correct value.

[speleato]

I agree that 2s is a long time, which makes me think that something about your design is making it take that long.

Can you explain the FPGA VI? Why do you wait for all 8000 elements to be transfered to the FPGA? What is the Flip Flop for?

I haven't run it, but I share the question Dragis asked where it's not clear to me how more than one element is read from the "From Host" FIFO and transferred to the "To Host" FIFO.

Sebastian