Hi, I have an application in which I need to collect a lot of (50+) narrowband spectral components from an analog input datastream. I am using a PXIe-7965R FlexRIO FPGA board and an NI-5732 digitizer adapter module. There are a couple of ways I could implement this, but I'm not sure which would be more efficient or plausible. The input datastream would be a 1D array of either 16kS or 32kS from the digitizer, and I would need to filter very specific frequency components out and sum them. Here are the options I was considering:
1. Take a Fourier transform of the data set, then generate a binary mask to multiply with the Fourier transformed result, effectively giving only the desired frequency components. The product array could then be summed for the final result. The main problem with this method is that I have not been able to find an FFT IP for LV FPGA that supports 1D input arrays longer than 8 kS. Does one exist? Additionally, there is the question of whether a longer FFT could fit on the FPGA.
2. Create a lot of time domain narrowband filters (Butterworth?) and sum the results of all of the filters. I am not sure if this would be less resources than the FFT or not. It would certainly be more cumbersome, considering I would have to implement 50+ filters on the input sequence.
I'm very new to LV FPGA and FPGAs in general, so I'd appreciate any comments or suggestions anyone may have for my application.
I do not have any experience with FPGA so I am not addressing those aspects of your questions.
Have you verified that your numbers make sense? When I read your question my gut reaction was, "Can this even work?" "Is there enough data in 16 K or 32 K samples to extract that inforamtion?" What is the range of frequencies in the datastream? What is the sample rate? What is the required resolution? Can two or more components ever be closer together than the specified resolution? (Even if you do not care about resolving them in this case, which you cannot, overlapping signals might complicate the analysis). Are the frequencies of the components known? If so, are the frequencies rational fractions of the sample rate? Do any of the components vary in amplitude or frequency during one sample set?
I think that an FFT-based system will be the way to go. Multiple filters with narrow enough bandwidths would be a real mess, hard to get working well, and not versatile.
Thank you for the response. I have in fact tested the FFT and binary mask method and it works well, but I could not go much below 16K-32K samples due to problems with frequency resolution. I have previously done this with a standard digitizer and done the processing in LabVIEW using the FFT/binary mask approach I previously mentioned. I am currently trying to speed up the processing, which is the reason for the FPGA. However, I need to find an FFT IP that can handle a 32kS array if this method is going to work. I agree that the FFT-based approach will be both less complicated and more versatile, but it will primarily depend on whether the FPGA can handle it and whether it is more efficient (concerning the FPGA) than a bunch of digital filters.
I am not sure if you are still interested, but I have an alternative suggestion that may be practicable. It will work best if there are only have a few frequency components that you care about but it could provide very fine frequency resolution. The idea is to multiply your input signal by a sine (and cosine) wave at each frequency that you need. Then you filter each output with a low-pass filter (e.g. sum and dump or CIC) before adding up all signals. The frequency resolution is determined by the LPF corner frequency (inverse averaging time). I guess you could think of this as only calculating the FFT bins that you need.
I found the code I needed for this problem. As it turns out, Labview does support a Xilinx FFT core that supports up to 65kS. It comes with LV 2011 FPGA, but a version for LV 2010 FPGA can be downloaded.
Quadrature demodulation (the technique you describe) is certainly a good method for filtering out specific frequencies, but would be a bit impractical for the 50+ frequencies I need to filter out. That would require the generation and multiplication of 50+ sine and 50+ cosine waves, along with filters afterwards. And since the multiplication would shift all frequencies in the signal according to sum/difference frequency mixing, I would have to give each of the multiplications an unaltered (original) signal. They could not be done in succession with a single input signal. While this could be done, I think it would be quite cumbersome. Thanks a lot for your reply!
I was hoping to revive this post because I'm running into something very similar. The express FFT that comes with the FPGA is limited to 8192 points max. I need to go bigger... like the 16kS mentioned in this post.
Ryan, would you mind sharing the code you said you found that can handle 16kS or higher? Or perhaps someone could tell me where I could go about looking for it? I'll probably need to find a hanning window vi that can also support the 16kS. I'm running LabVIEW 2011.
Hi, Jblee. LabVIEW 2011 comes with the Xilinx Core IP for large FFTs, I believe. Look under the FPGA palette and go to Xilinx Core IP. You can then find "FFT 8.0" somewhere in there. It's description can be found on this page. I have not found an appropriate Hanning window for this IP.
thanks for that link. The FFT Express VI is nice and easy to use but limited so I am going to try this IP. I've been playing with this Xilinx core FFT but am running into some problems with wiring. I followed the data spec sheet I found online for the various pins but labVIEW says I have some bad terminals. Would you or someone else be able to share some sample code that uses this Xilinx FFT IP block? It would be most appreciated.
I could not personally find an example of using the Xilinx FFT IP block. However, there is an NI Community for Xilinx IP that you might want to post your question to as well as these LabVIEW users might have an example for you. There was also a suggestion there that you can create your own IP and import it to LabVIEW FPGA which might also be an option for you.
Hope This Helps,