FPGA Evaluation how many ticks for code section

[e1ding]

Dear LV enthusiasts,

Is there any way to determine how many ticks are needed for the execution of a for-loop or a VI? The code isn't running as fast as required, and I would like to identify the bottleneck. Maybe some simulation?

Thank you in advance!

[GerdW]

Hi e1,

place timing functions in your code to measure the execution time!

[wiebe@CARYA]

No answer to your question, but...

Put time critical code in a single cycle timed loop.

This ensures it takes 1 tick... It won't compile if it doesn't fit.

[ZYOng]

Use the LabVIEW FPGA Desktop Execution Node to get accurate timing in simulation mode.

[wiebe@CARYA]

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@ZYOng wrote:

Use the LabVIEW FPGA Desktop Execution Node to get accurate timing in simulation mode.

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First time I heart about that... 

I'll still stick to the SCTL whenever I can, so I hope I remember this tool if I ever need it.