FPGA Digital Input Negative Voltage

[Bertha]

What is the maximum negative voltage that the digital input on the FPGA can take without damaging it? I tried to look in the datasheet for the sRio 9636 and I can't find it.

Thanks

[tannerite · Accepted solution]

Hi Bertha,

The sbRIO-9636 has DIO only on the DIO (J502) and MIO (J503) connectors. This is a little different from other sbRIO-96xx variants in that others may have an RMC connector that has additional DIO.

The DIO and MIO 50-Pin IDC connectors are 3.3V pins, but they are 5V tolerant inputs as we have some protection on the IDC connector DIO. The VIL and VIH values are specified in the datasheet:

http://www.ni.com/pdf/manuals/373378d.pdf

These are the recommended operating conditions. If you are needing to know the maximum negative voltage to determine if your undershoot is acceptible, that number at an absolute minimum is -500 mV. I would recommend you choosing appropriate series termination resistors at your driver to minimize the undershoot, however. The same absolute minimum also applies to the 3.3V RMC DIO as well.