FPGA Derived Clock Rate Range

[SunJab]

Hi all,

I am using labview fpga 2011. I want to know what is the maximum and minimum fpga derived clock rate that can be speficied? Is it dependent upon the fpga target device? i'm using NI FlexRIO PXIe7965R.

thanks

[TheGeeze]

Hi,

The typical FPGA has a clock of 40 MHz and the smallest that can be reduced to is 2.5 MHz.  The largest clock is 346.666 MHz.  We must becareful when we talk about maximum clock speed tough.  Just because the system is cabable of producing a clock speed, does not mean that you can perform your desired operations at that speed.  It is highly unlikely that you will be able to compile your program at that speed.  Most programs will start running into issues at about 100MHz.  The only wat to truely know is to build your program and try to compile at the requested speed.  

Let us know if you have further questions.

Ryan

[SunJab]

ok.

According to the  'Virtex-5 FPGA Xtreme DSP Design Considerations' document, a fully pipelined DSP48E slice can be opearted at a maximum speed of 550MHz. I want to implement a multiplier using the DSP48E function in FPGA. If the largest clock is 346.666 MHz, that means there is no way i can operate the DSP48E slice at 550MHz???

[SunJab]

ok.

According to the  'Virtex-5 FPGA Xtreme DSP Design Considerations' document, a fully pipelined DSP48E slice can be opearted at a maximum speed of 550MHz. I want to implement a multiplier using the DSP48E function in FPGA. If the largest clock is 346.666 MHz, that means there is no way i can operate the DSP48E slice at 550MHz???

[TheGeeze]

You can implement a multiplier using the DSP48E slice.  But like all FPGA functions, your speed is always limited to you maximum clock speed.  So although that specific slice can operate at a faster clock speed, the fastest clock that we can provide using our hardware is 346MHz.  

Here is an example of how to use the HDL node for multiplication.  http://zone.ni.com/devzone/cda/epd/p/id/5959

Ryan

[SunJab]

Thnaks.