FPGA DMA FIFO, Communication Error

[JonathanJohnson]

Hello,

I am working with an PXI-7851R, and I am having a problem that I would like some help with solving. The problem occurs on a new computer running windows 10, which has a PCIe-8361 inside it. This connects to a PXIe-8360 controller housed in the chassis with the FPGA module. I am currently using labview 2015 SP1.

Although compiling, loading a bitfile to the FPGA and running it, front panel FPGA communication, etc, is working without issue, I am having a communication error when I try to use a DMA FIFO to stream data from the host to the fpga target. Basically the data is not able to be read from the FPGA side due to the communication error. I believe that this is not a coding problem, as the same problem occurs when using the DMA streaming example that comes with labview. Additionally, when I switch the PCIe-8361 card to a different computer, the FIFO runs as expected without error using the same code.

Here is the error I have been getting:

I have tried updating all software version, drivers and firmware for the NI hardware, as well as updating the computer BIOS to the latest version (which solved a similar problem for some people), but the problem still persists. Does anybody have any idea how to solve this problem, or what may be the root cause? I'd appreciate some guidance.

Regards,

Jonathan

[Terry_ALE]

When you mention "front panel FPGA communication" are you directly running the FPGA VI from the computer?

[JonathanJohnson]

Yes, for example, if I create an FPGA targeted VI that has a control or indicator on the front of the VI, I can run that VI from the computer, and the controls and indicators work as expected (e.g. controlling the analog I/O on the PXI-7851R module)

However, when I attempt to programatically open a reference to an FPGA VI and write to the host-to-target DMA FIFO, the FIFO reports 0 elements remaining, and I receive the errors mentioned above. Additionally, the host VI freezes and I have to restart the computer, since I cannot stop the host VI. Here, the whole computer is not frozen, just the host VI is stuck in an endless loop of attempting to reset.

Hopefully this sheds more light on my problem so that somebody may be able to help. If anybody has an idea for what to try in order to troubleshoot this problem, please let me know. I'll attempt to work on this more today...

[JonathanJohnson · Accepted solution]

After working on this problem again today, I think that the issue is now solved.

It seems that it was a BIOS issue, meaning that the PCIe-8361 card was not able to function correctly. By installing the "MXI-Express BIOS compatibility" software from NI, and setting the BIOS compatibility mode DIP switch on the PCIe-8361 to ON, my FIFOs now function as expected.

[Terry_ALE]

Seems like you are using Interactive mode (https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/ifp_comm/).

I find this to be quite limiting.  Though it can be good for spot checking it is best to programmatically open the FPGA VI and interact with it that way.

Looks like it was a BIOS issue.  Never saw that before but good that it has been figured out.