FPGA Controlling from an external control

[Edwarde]

Hi, I would like to control Host.vi from FPGA. For example I have a numeric control on FPGA.vi and when i change its value it needs to effect FPGA.vi then Host.vi.   How can I do this?

I tried create sub.vi on Host.vi but it can not be supported. I read FPGA from Open Reference Vi.

Thank you

[Sam_Sharp]

I don't think your question is clear enough - can you post your VIs or give a bit more description of what you are trying to do?

On your FPGA VI, you can have a front panel control/indicator which you can read (by polling it periodically) on your Host VI using an FPGA I/O node and based on the value, perform different actions (e.g. by detecting a change).

If you don't want to poll for the change (which uses CPU cycles), on some FPGA targets you can generate interrupts and use the 'Wait on IRQ' method on the Host VI to acknowledge the interrupt and perform your action. You can also do something similar with a Target to Host FIFO.

[Edwarde]

For example,

In FPGA vi, I have a controller which name is Value. When I compiled FPGA vi, and then run the Host vi. It reads FPGA Reference and gets controller value but when I change controller value, host vi behaves like first value.

Example: FPGA Controller Value: 1000 then run Host.vi it reads this value and acts rightly. Then I change value of controller but it continues to show same value.

How can I do that?

[Sam_Sharp]

How are you changing the value on the FPGA controller? Are you running the FPGA VI interactively and changing it from the front panel or are you setting it programatically from the host VI?

I think you need to show a simple example of how you have structured your code on the host/FPGA VI.

[Edwarde]

I have added my Vis.

[Sam_Sharp]

So I think you have changed your code since you started to use a FIFO instead of reading/writing from a control/indicator.

What rate is the loop on the FPGA running at? If it's running very fast then you will be filling up the FIFO much faster than you can read the elements on the host side - check the 'Timed out' output on the FPGA, check the elements remaining and try reading more elements on the Host VI (you can do a read of 0 elements to find out how many elements are in the FIFO and then read that many)

Also (as an aside), FIFOs are 32-bit in size which means that sending your 1-bit boolean is wasting 31 bits. You would be better off shifting the booleans into a U32 and then putting it into the FIFO every 32 cycles.

[Edwarde]

The main thing is that I am creating a signal from square signal wave and write the signal values to FIFO. Then in host vi I am reading these values and when I change Frequency control it needs to change the number of square waves on Waveform graph but when i choose 1kHz and 1000kHz all this similar in waveform chart. Can you help me how I can correct this?

Summary:

• Produce square wave from FPGA which clock rate is 40 MHz. I added frequency control and multiply with 1000 and divide to 40Million to find periods/ticks then send to the Square Wave Generator. Then sent them to FIFO.Write method. 
• I run Host Vi and change the Frequency value which is taken from Read/Write Control component.
• The problem is that I can not see the difference between 1kHz and 1000kHz on Waveform Chart. What is the problem?

Thank you very much.

[Sam_Sharp]

I'm not sure as I've never used that square wave express VI before, but having a quick look I think you need to either put the VI into a timed loop (either with timing, or as a single-cycle timed loop - note you have to configure the express VI for this) or add a loop timer to your FPGA VI so that the square wave VI knows what rate to run at.

[Edwarde]

Hmm, you can be right. If I add loop timer, square wave vi can understand the frequency changed or not. Am I right? Other question if I add loop timer, does it affect signal transmission because I want to send data from FPGA to Host as fast as?

Thanks.