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FPGA Compilation Error - Kistler KI 5171A4

Hi,

 

I'm building up a hybrid cRIO build, with the FPGA for a view non-NI modules, and other high speed data capture. One of those modules is a Kistler 5171 A4. Currently, I have no code in the fpga vi relating to the Kistler module. When I'm compiling I'm getting a Timing Violation Error, with a load of non-diagram components, that relates to model. 

 

Capture.PNG

 

I don't really have a clue where to go for debugging this as an issue, as without being able to see anything on the VI, I can't understand what might be causing the problem. Can you think of anything I should be considering / looking at?

 

Cheers,

Peter

 

 

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Message 1 of 6
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You'll have to look in the manual to be sure, but I think those vi's can't be used in single cycled timed loop.

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Hi Wiebe,

 

Thanks for the reply. Yes that is what I imagine too, but what's weird is that VI isn't being used on the FPGA vi, and nor do I have a SCTL (attached is the FPGA.vi). Unfortunately, there isn't that much material provided with the module. I'll have a dig around and see what I can find. 

 

Kind regards,

Peter 

 

 

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Can you double-click those tree items? IIRC they should highlight the offending node.

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Turns out they are in my project (I assume these must get automatically added when the module is found in the cRIO):

 

Capture.PNG

Unfortunately, the VI is password protected, so I'm going to have to contact Kistler. 

 

Thanks,

Peter

 

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Hi Peter,

Did you get anywhere with this? It seems like Kistler have discontinued the module and aren't supporting it in newer versions of Labview...

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