FIFO

[Betty Boop]

Hello!

I’m finally successful in passing an integer from the FPGA.vi to the Host.vi through the FIFO. I just changed the data type of the FIFO. Thank you very much for the suggestion! 😄

I’m now trying to input an array from the Host.vi to the FPGA.vi through the Read/Write Control of the FPGA Interface palette. My first attempt was unsuccessful. In my second attempt, I took note of Denn_Mann’s advice of using interrupts. I got some numbers in the FPGA.vi ‘array’ indicator which is a good sign. However, the elements of the array appeared to be rounded-off when compared to the actual elements written in the Host.vi. I checked the data type of the elements of the array in the Host.vi. All are set to signed fixed-point representation with word length equals 16 bits and integer word length equals 9 bits. Attached are the screenshots of the Host.vi and FPGA.vi. Do you have any suggestions on how I can fix this problem?

Thank you very much for your time! I really appreciate it. 😄

[dan_u]

Do you see the small coercion dots? These tell you that the data types don't match.

Anyway, what you see on the front panel of the FPGA VI might just be due to the display format. The array indicator seems to have the correct values so real sig1 must have the correct values as well.

You can adjust the display format by right-clicking a number in the array.

[Betty Boop]

Hi! Thank you for your reply!

I’m currently working on removing the small coercion dots you mentioned in your last reply.

For the FPGA.vi, I am able to do this by setting the properties of the ‘array’ indicator to ‘adapt to source’.

For the Host.vi, I’m having some problems. I know for a fact that the FPGA operates with integer or fixed-point numbers. Since my application deals with fractional numbers, I use fixed-point representation. I thought that the only thing left to adjust are the word length and the integer word length. I tried increasing/decreasing both of them but I’m still unable to remove the coercion dot. I need to remove it because it is affecting the data I'm passing (i.e. the 4th element of the array is actually 3, but I only get 2 in the FPGA.vi).

Thank you! 🙂

[dan_u]

I don't think you can get rid of the coercion dot on the host when writing to the FIFO. This is caused by a variable size to fixed size array transformation. The host only supports variable size arrays, the FPGA only fixed size arrays.

You just have to make sure the FXP type matches (signed/unsigned, word length, integer word length). I'm sure this currently does not match. The FXP type on the host seems to be different than the type in the FIFO.

It seems the FXP range on the FPGA (and the FIFO) is -2..~2 (so signed with 2 integer bits). On the host you definitely have more than 2 integer bits.

[Betty Boop]

Hello!

You are right. I tried inputting elements of the array which are less than -2 and greater than 2, and the FPGA.vi interprets them as -2 and 2 respectively.

I checked the display format of each element of the array. All are set to fixed point, signed, word length equals 16 bits and integer word length equals 9 bits. And then I checked the data type of the FIFO. It is also set to fixed point, signed, word length equals 16 bits and integer word length equals 9 bits. The setting for ‘real sig1’ and ‘array’ inside the FPGA.vi is only for the dimension and size of the array which are 1 and 5 respectively.

Do you know what else is needed to be set/adjusted so that the FXP type on the host matches that on the fpga?

Thank you! 😄

[dan_u]

Currently you're not using a FIFO so no need to check that.

What's the configuration of the real sig1 array on the FPGA? I think this has an incorrect FXP data type.

Btw, all elements in an array have the same representation. No need to check each element individually.

[Betty Boop]

Hi!

When I right-clicked the ‘real sig1’ and selected Properties, the only configurations I could set are the dimension and array size which I choose to be 1 and 5 respectively. I also checked the representation by right-clicking again and it is set to fixed-point. I don't know where to adjust (if I can even adjust) the word length and integer word length since the settings are for an array as a whole (not per element).

[dan_u]

You have to right-click an element to change the data type, but the change will apply to all array elements.
Probably you should get familiar with some of the LabVIEW basics before trying to work with FPGAs...

[Betty Boop]

Hi, Sir!

I assure you I understand how to adjust the data type of each element.

I think I know what I’m missing here. When I adjusted the FXP type on the FPGA, I only looked at the block diagram of the FPGA.vi. Since in my block diagram, the arrays are written as arrays (the elements are not shown as in the attached screenshot), I would always have the dimension and size as the ONLY configurations which I could adjust. I realized that the elements are shown in the front panel as in the other attached file. This is where I could adjust the configuration of the elements. I must have overlooked this.

I shall test my revised code as soon as possible.

Thanks for the help! I appreciate it. 😄

[dan_u]

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@Betty Boop wrote:

I assure you I understand how to adjust the data type of each element.

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Again, you can't adjust the data type of each element individually. All elements in an array have the same data type.

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I think I know what I’m missing here. When I adjusted the FXP type on the FPGA, I only looked at the block diagram of the FPGA.vi. Since in my block diagram, the arrays are written as arrays (the elements are not shown as in the attached screenshot), I would always have the dimension and size as the ONLY configurations which I could adjust. I realized that the elements are shown in the front panel as in the other attached file. This is where I could adjust the configuration of the elements. I must have overlooked this.

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That's excatly what I mean when I'm saying you should learn the LabVIEW basics first...

How to set data types is really basic.