FIFO

[Betty Boop]

Hello!

I'm new in using DMA FIFO. I need to input an array into the FPGA VI. And then inside the FPGA VI, I get the sum of the elements of the array. I "send" this sum back to the Host VI. This should be simple. Unfortunately, I'm having problems. It seems that I'm not able to input the array into the FPGA VI. This is because nothing reflects in the "array" indicator inside the FPGA VI. Attached are the pictures of the Host VI and FPGA VI. Please assume that I have already set the FPGA target so that there is no broken line in the Host VI block diagram.

Thank you so much for your time! 🙂 

[Rachel D]

Hi there. Thank you for posting on the discussion forum.

I have a few questions/suggestions for you to consider that may be helpful as you try to resolve your issue:

1. Have you been able to use the FIFO successfully in any capacity? Try passing one piece of data through the FIFO from the FPGA.vi to the host.vi.
2. Have you tested the FPGA.vi directly, i.e. have you tried to run the FPGA.vi on the FPGA alone? Does that work?
3. You could also try putting a while loop in the FPGA.vi.

Best,

[Denn_Mann]

Your code looks good.  What I belive is missing is the synchorinzation setup between the FPGA code and the Host VI.  You can set an IRQ in the FPGA side and have it wait to be acknowledged by the Host VI before the FPGA can begin its accumulation process.  This FPGA IRQ would be placed just before the Array is received in the FPGA code (I would use a sequency structure to force the FPGA code to wait with one sequence frame around the IRQ and the next on the array control).  Now, the other half of this IRQ will need to go on the Host VI in order to acknowledge this FPGA IRQ.  In your Host code, I would place this right after you have sent the array to the FPGA.  Remember to set the FPGA IRQ to TRUE when it asks if it should wait to be acknowledge, and obviously, DO ACKNOWLEDGE this IRQ on the Host side.

This should get your basic code working 🙂

Have a nice day!

[taper]

I second making sure the FPGA is running before trying to write the values.

If that doesn't work check your arrays.  You need fixed array sizes on the FPGA, I haven't worked with it enough to say exactly what will happen if you try to write more than that from the Host.

[Betty Boop]

Hello, Rachel!

I followed your advice and confirmed that the FPGA is working by running the FPGA.vi on the FPGA alone. This VI is without any data passed through the FIFO from the Host.vi to the FPGA.vi and vice versa.

When I tried passing one piece of data through the FIFO from the FPGA.vi to the Host.vi (as you suggested), I was unsuccessful. Attached are the screenshots of the Host.vi and FPGA.vi. My goal there is to simply pass the number 7 from the FPGA.vi to the Host.vi. However, I had weird results on the Host.vi. I got approximately 2, instead of 7. Do you have any advice on how I can fix this?

Thank you very much for your time! 😄

[Betty Boop]

Hi, Denn_Mann!

I’m currently working on it. 😄 I’ll let you know as soon as I finish editing and testing the code with your suggestions on it.

Thank you very much for your time! 😄

[Betty Boop]

Hello, taper!

Like my reply to Rachel, I am able to confirm that the FPGA is working. However, when I tried passing one piece of data through the FIFO from the FPGA.vi to the Host.vi, I was unsuccessful. Attached are the screenshots of the Host.vi and FPGA.vi. My goal there is to simply pass the number 7 from the FPGA.vi to the Host.vi. However, I had weird results on the Host.vi. I got approximately 2, instead of 7. Do you have any advice on how I can fix this?

Thank you very much for your time! 😄

[dan_u]

What's your FXP configuration? On the FPGA you write an integer 7 to a FXP input of a FIFO. If the FXP configuration only has a range up to ~2 (eg. <+-,16,2> or <+,16,1>) the integer value will be coerced.

Adjust the FIFO data type to match the data type you want to send.

[Betty Boop]

Hello!

The 'array' and 'yay' indicators in the Host.vi are set to 'adapt to source' configuration.

Sorry, I'm really new in using FIFO. How do I ajust the FIFO data type to match the data type I want to send? I tried 'right-clicking' the FIFO 'box' in the FPGA.vi block diagram, but I couldn't find the adjustment of FIFO data type.

Thank you very much! 😄

[dan_u]

The FIFO data type is defined in the project. Double-click the FIFO in the project and define the data type in the properties window. If you work with I32 use that data type for the FIFO instead of FXP.