FIFO's and reading vs. writing

[wrath_of_con]

Howdy folks,

I have read in the literature

http://zone.ni.com/devzone/devzoneweb.nsf/Opendoc?openagent&95659432CC4261CA86256AB8004F3EF8  that...

To avoid overwriting elements, you need to either make sure that the reader will always read elements from the RT FIFO faster than they are written, or you need to ensure that the RT FIFO is large enough to contain the elements that are written to it while the reader is unable to read. You also need to make sure that the reader has the ability to catch up to the writer. In other words, the reader needs to be able to read points from the RT FIFO faster than the writer on the average, and the RT FIFO needs to be large enough to store elements while the reader is busy.

My question are...  if I have a time critical loop that is writing the FIFO's and normal priority loop reading the FIFO's, both at 1ms rate, how would I be able to read the FIFO faster than I am writing to the FIFO?  Wouldnt the the time critical loop take precedence over the normal priority loop and write to the FIFO whether it has been read or not?  How would the reader 'catch up' to the writer?

I guess the other option is to make a large FIFO, but how would one determine the necessary size?

Thanks in advance!

- Conrad

On a side note - who can guess the song first?

So many things I think about

When I look far away

Things I know

Things I wonder

Things I'd like to say

[DimensionFinder]

Hi Conrad:

You will use the Time Critical Loop to collect data and write that data in to a FIFO. The Normal Priority Loop will then read the data from that same FIFO.

What the document is trying to say is, lets say that we are running a time critical loop with a wait function in it of 100 ms. Then lets say that the code in the loop takes 50 ms to execute. We still have 50 ms remaining before the loop executes again. During the remaining 50 ms, the processor switches over to the Normal Priority Loop where data is read from the FIFO. Now in this loop we need to specify a wait time of less than 100 ms, maybe something like 10 ms so that we read 5 data points during the 50 ms.

So to answer your questions, the Time Critical Loop will only take up your processor when it is executing, however, while it is asleep (during the wait period in your whie loop) your processor will devote time to other processes.

Let me know if this answers your question.

Best Regards,

Jaideep J.

[wrath_of_con]

Thanks for your info Jaideep J.

I also came across a RT FIFO with Catch up example, that illustrated whats going on fairly well.

Here's some background...

We are using cRIO (limited timed loop rate of 1KHz). We must acquire data every millisecond and have this data recorded to a file - we CANNOT miss even one read and all the data recorded must match up - we seem to have been missing some data while writing the file.

We have been using a timed loop of higher priority to acquire data and write to two FIFOs and a lower priority loop to read from these FIFOs and write to two files.  But during post-processing we have noticed some data points missing from the files.

Any suggestions? Maybe a catch up loop during the write as described in the Catch Up example? Maybe a more efficent way to write files?

Thanks again.

[DimensionFinder]

Hi Conrad:

Are you writing to the FIFO faster than you are reading? You said that you are writing data every 1 millisecond. What is the speed at which you are reading from the FIFO in the Normal Priority Loop at? Have you tried speeding up this loop. Also, are you checking to see if the FIFO is empty in this loop?

Lastly, I would recommend looking for some example programs which should be available by going to Help>Find Examples>Hardware Input and Output>FPGA from the menu bar that you see when you open a blank VI.

Regards,

Jaideep J.