FFT

[altenbach]

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@erezg wrote:

But I think I found the reason.

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Well, that's exactly what I meant with my last sentence above. 🙂

(I was curious if the subVi does anything fancy, such as integrating the peak, but I guess it is quite simple. 😉

[Henrik_Volkers]

If you have a (nearly) sine frequency and you want to measure the amplitude (+frequency+phase) of that frequency (small band, just that frequency!) I suggest to try the extract single tone information.vi .

it also works with FFT but compensate leakage ..  feed it with more than 10 periodes and you get nice results.

here  I made a vi to measure and monitor 50Hz linefreq with the soundcard (OMG 2010 :D)  .. easy to adapt to 60Hz  😉

[erezg]

thanks for the support.

BTW, the "extract single tone information.vi " works great 🙂

will save me a lot of time doing the integration...

thanks All,

[altenbach]

Well, you never said that you are only interested in one dominant "tone". I thought your example was just a demonstration of the "problem". 😉

If you already know the frequency and are just interested in the magnitude even simpler solutions are possible. Also note that if you actually want to monitor e.g. changes in amplitude over time, you might want to stick with smaller intervals to get better time resolution in the result.

What are you actually trying to measure here? What is the experiment?

(Again, what is the name of the toolkit where you got that subVI? Its code seems a bit stale.)

[GerdW]

Hi Christian,

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@altenbach wrote:

(Again, what is the name of the toolkit where you got that subVI? Its code seems a bit stale.)

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It's coming with LabVIEW:

[altenbach]

No it does not  come with LabVIEW, even LabVIEW professional! It seems to be part of the FPGA module, which I don't have installed on my current computer.

On what kind of hardware are you (i.e. OP) running this?

I am still curious what problem they are trying to solve overall. 😉

[GerdW]

Hi Christian,

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@altenbach wrote:

No it does not  come with LabVIEW, even LabVIEW professional! It seems to be part of the FPGA module, which I don't have installed on my current computer.

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Oh, learned something new today… (Yes, I have the FPGA module installed.)

(Rethoric question: Why does that VI require the FPGA interface when it only uses DBL datatypes all around? Which FPGA interface supports DBL wires? Just from looking at the VI I never would guess it comes with the FPGA module…)

[altenbach]

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@GerdW wrote:

(Rethoric question: Why does that VI require the FPGA interface when it only uses DBL datatypes all around? Which FPGA interface supports DBL wires? Just from looking at the VI I never would guess it comes with the FPGA module…)

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Exactly, I was confused about that too... Why do they divide a I32 by 2.0 (DBL), then immediately convert back to I32 when a simple right-shift would probably have been sufficient? Why are there two DBL array inputs for RE and IM if a single CDB input would have been more reasonable, eliminating the test to see if both have the same length? etc...  Oh well. 😄