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Error in the Timing Violation Analysis

Hello,

 

I've got an unexpected error after compiling a FPGA project:

 

TimingViolationAnalysis.png

 

The total delay of the path (8.32ns) smaller than the requirement (8.33ns) and the delay of the path, which consists of the SumSign VI (7.08ns) and a Non-diagram component (0.69ns) should be 7.08ns + 0.69ns = 7.77ns and not 8.32ns. Does anyone have an explanation where the missing time is coming from?

 

 

Im using Labview 2011 (32bit), Xilinx 12.4 Compiler, Windows 7

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I can't exactly help but I got a timing error today also where the timings simply didn't add up.

 

I'm using LV 2012 SP1 and Xilinx 13.4.

 

Shane.

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Hi,

 

I have never seen it before. Could you post your VIs? 

 

Regards, Fabian

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I certainly can't.  It would mean exposing our and others IP which we are contractually unable to do.

 

Shane.

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