I just copied my post from the Xilinx forum asking this same question so keep that in mind but it should make sense. I'm working with a CRIO 9014 with a 9104 expansion and 9401 cards. Thanks!
Background:
Device: xc2v3000-4-fg676 (Spartan III)
The device is located on the backplane of a cRIO 9014 by Nationa Instruments. Most of the code is made by LabVIEW however I used a 'HDLNODE' block so I could code in my own HDL.
I am trying to create a random number using the UNIFORM function from IEE.MATH_PACK to create a random number that I then scale to 0-127 (int) and convert to an array. I use it to drive 7 IO bits that need to all randomly toggle. When I keep my call to the UNIFORM function I get an error back from the Xilinx compiler. If I replace the UNIFORM call with a constant REAL value then I compile with no problems.
Does anyone know for sure if UNIFORM is synthesizable? If so, have you used it on the same FPGA?
I have attached the error and have my code below. As I said, if I comment out my line of code calling on UNIFORM the code generates just fine.
library ieee; use ieee.std_logic_1164.all;
library ieee; use ieee.math_real.all;
library ieee; use ieee.std_logic_arith.all;
entity my_code is
generic(
ClockFrequency : Integer := 40000000
);
port(
clk : in std_logic;
reset : in std_logic;
enable_in : in std_logic;
enable_out : out std_logic;
enable_clr : in std_logic;
tf1 : out std_logic_vector(0 downto 0);
tf2 : out std_logic_vector(0 downto 0);
tf3 : out std_logic_vector(0 downto 0);
tf4 : out std_logic_vector(0 downto 0);
tf5 : out std_logic_vector(0 downto 0);
tf6 : out std_logic_vector(0 downto 0);
tf7 : out std_logic_vector(0 downto 0);
tf8 : out std_logic_vector(0 downto 0)
);
end my_code;
architecture arch of my_code is
signal random_bits_int :integer;
signal random_bits : std_logic_vector(7 downto 0);
signal div_clk : std_logic;
signal temp : std_logic;
signal cnt : integer;
begin
div_clk_proc : process(clk, reset)
begin
if(reset = '1') then
temp <= '0';
cnt <= 0;
elsif(clk'event and clk='1') then
if(cnt = 10000000) then
temp <= not(temp);
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end process div_clk_proc;
div_clk <= temp;
create_var : process(div_clk)
variable S1, S2 : positive;
variable rand_out : real := 0.0;
variable OUT_PUT :integer := 0;
begin
if(div_clk'event and div_clk='1')then
-- Create Random number between 0 and 1
uniform(S1, S2, rand_out);
--rand_out := 0.6;
-- Convert number from 0 to 7-bits (127)
OUT_PUT := INTEGER(rand_out);
OUT_PUT := 127 *OUT_PUT;
random_bits_int <= OUT_PUT;
end if;
end process create_var;
random_bits <= conv_std_logic_vector(random_bits_int,8);
tf1 <= random_bits(0 downto 0);
tf2 <= random_bits(1 downto 1);
tf3 <= random_bits(2 downto 2);
tf4 <= random_bits(3 downto 3);
tf5 <= random_bits(4 downto 4);
tf6 <= random_bits(5 downto 5);
tf7 <= random_bits(6 downto 6);
tf8 <= random_bits(7 downto 7);
enable_out <= enable_in;
end arch;
