Error -50400 Open FPGA reference error

[rex1030]

I am getting the following error when I run my code on my crio system:

error code -50400

"Error -50400 occurred at Open FPGA VI Reference in 9236 and 9237 Take Measurements.vi->Set Shunt Cal Get Average Msmt.vi->Belle Glade CRIO.vi
Possible reason(s):
The transfer did not complete within the timeout period or within the specified number of retries."

 I have combined the 9236, 9237 and 923x continous acquisition examples into a program to read from these modules contiuously as well as shunt cal and null.

I am using the NI crio-9014 RT controller with the NI-9104 fpga backplane and the program is accessing a 9236 module and a 9237 module via FPGA programing (not scan mode which isnt supported on 9236 at the moment).

The crazy thing is the error occurs at the Open FPGA Reference before I even have a chance to do anything else. I have reformated the crio and reinstalled the drivers/software. I have made sure the 'Automatically close VISA sessions' option is unchecked. I have recompiled the fpga file many times, with no errors or problems. I even deleted the Open FPGA Reference and created a new one. Still getting this error.

Should I post the project as a zip file

Using Labview 8.6.1 April 2009 update on both PC and cRIO device. 

[David_L]

Are you sure that this error comes from the Open FPGA Reference? This error usually is associated with DMA FIFOs.  However it might be possible that it is caused from taking too long to download the bitfile.  Have you tried manually downloading the FPGA bitfile before running the Host VI?

[rex1030]

Could you please elaborate on manually downloading the bitfile?

[rex1030]

Could someone just elaborate on the DMA fifos error if you cant elaborate on the other. I didnt find a single document on this error anywhere and any and all information you could give would probably help me narrow down the error. I really appreciate your help because I need to fix this problem. Maybe I should open a support ticket tomorrow.

[David_L]

In your project you can right-click the FPGA VI and select download.  This will compile it if not already compiled and then download the bitfile to the cRIO.