Does using FPGA IP reduce compile time?

[cgibson]

Hi Folks,

Just like the subject says. If I take some of the VIs in my FPGA project and turn them into IP, will that help the FPGA code compile faster?

Does this require the FPGA IP Builder?

Where can I find out more? (Yes, I have tried Google.)

[Terry_ALE]

Can you clarify?  Does IP (Intellectual Property) mean VHDL or IP Builder?

What is current compile time?  Usually compile time is not we look to reduce.  We usually try to get compile to complete (fix on resources or meet timing).

[cgibson]

Hi,

We have FPGA code that is taking around 3 hours to compile. It has a bug. The 3 hour compile time is a real crimp in the usual LabVIEW debug process.

I was thinking about this and wondered if the IP features for the FPGA where in some way precompiled and making portions of the existing code into IP would help speed up compile so we could get faster cycle time on our debugging.

Does this make sense?

[Terry_ALE]

Still not enough info.

3 hours may mean you are using a lot of BRAM somewhere and routing could be taking a long time.

Can the bug be tested in simulation mode?

[cgibson]

Hi Terrry,

The bug is in code that calculates velocity and acceleration from an encoder signal. We would need to simulate the encoder input and my past experience with the FPGA simulation modes tells me getting this to work right can be challenging. It may be the best way to go. Since we are a team, we are taking multiple approaches.

I appreciate your eagerness to help. Do you know the answer to my initial question about the FPGA IP?

I think the best way for me to get debug help would be to make another post with a relevant subject and a detailed description of the bug. That isn't what this post is about.

[Terry_ALE]

My question to your original question needs clarification: "Does IP (Intellectual Property) mean VHDL or IP Builder or something else?"  Even then, the question and answer are too hypothetical.

Whatever IP this is replaced with is in your case, debugging this way is not efficient at all.  Put the code with the math, add to subVI, run in simulation and try various inputs.  Probably fixed point math is off or something like that.

Record the sensor by streaming to a DMA-FIFO and play back that data into the above VI.  Make some kind of test bed.

[cgibson]

I do not currently have any IP. The FPGA code is all LabVIEW.

The idea would be to take some of this code that is not in the path of the bug and convert it to IP. I presume this would be via IP Builder.

So would taking some VIs in a larger FPGA application and converting them to IP have any effect on the compile time?

Maybe a different way of asking the question will help. Is IP, made by IP Builder compiled at all? Or is it at a high level of abstraction to allow the final compile as much latitude as possible?

[rolfk · Accepted solution]

What you are looking for is the term “synthesized” and I think the answer is no. Synthesizing is the process of mapping the higher level definition such as VHDL or Verilog or LabVIEW intermediate VHDL code into a specific fabric by translating the HDL description into a low level netlist and then the actual binary description map. This is also the most time consuming part, the higher level translation from LabVIEW diagram to the intermediate VHDL description is in comparison very fast.

So you would need to be able to add fully synthesized code blocks to your “program” but that defeats the idea of abstracting away the actual hardware details. I’m not sure there is a way to integrate fully presynthesized blocks into LabVIEW FPGA but I kind of doubt it.