You need to look at the relative speeds of your FPGA loop and your RT loop - they're not tied together in any way. There's no guarantee that the RT code will read the indicator once for each time the FPGA writes to it, unless your FPGA loop runs much slower than the RT loop. The front panel indicator or control is useful for transferring data for which only the most recent data is important. If your FPGA loop runs faster than your RT loop, the DMA transfer allows you to read multiple points at once and process them together, so that the RT code can keep up with your FPGA even though the loop cycle time is slower. If your RT code still can't keep up with the FPGA then you're sending too much data or processing it inefficiently. Again, being able to see your code would make it a lot easier to provide useful advice.
