DMA FIFO Host to Target FPGA

[Junli]

Hello every

I need a DMA FIFO Host to Target FPGA for my projet, I found few examples. does someone have some ideas how to manage the FIFO considering the following issues:

1. For the Host, How to avoid overflow? is thers a VI which can do this?

2. For the Target FPGA, how to avoid underflow?

3. for FPGA, is there any strategy allowing the FPGA to process data in the FIFO at a maxium speed.

4. If the Host is offline, How should the Target FPGA react?

5. If the Target FPGA is offline, How should the Host react?

Thanks in advance

Junli

[Jacobson-ni]

Junli,

Examples are a good way to understand how to  implement something in LabVIEW.  If you have more in depth questions about best practices for embedded development, I would suggest taking a look at the High-Performance FPGA Developer's Guide and the Compact RIO Developer's Guide.

http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf

http://www.ni.com/pdf/products/us/fullcriodevguide.pdf

The first will answer some of the questions you have about throughput, underflow, and overflow while the second will help with the higher level questions such as, "How should I react?".