Hi,
I'm new at using the Digital Filter Design Toolkit. My goal is to create a Decimation Filter that's going to be used in a cRIO FPGA target later on.
I want a decimation factor of 5.
If you have a look on the code joined, it seems to work pretty well in simulation.
But, I've 2 questions :
* I don't understand how the FXP output is calculated. In fact, I would like to get an iwl of 4 for the output and not 2. Do I have any way to specify it, to constraint it? I'm suppose to inject a signal coming from a cRIO-9234 module (FXP, 24,4) so I'd like that the output would be the same. Otherwise, I assume I may face saturation if the signal goes up to 5V at the input, it would clamped my output but that's not the case if I change the amplitude of the input signal from 1 to 5. I believe I'm missing a key-point.
NOTE: I don't use the decimation filter shipped with LV-FPGA because I don''t have the phase information for the filter shipped.
* I don't understand why the gain is about 0.5. How is-it calculated or specified? I'd like a gain of 1.
Best regards.
Vincent RUAULT
