Could someone explain this FPGA i/o timing issue?

[Intaris]

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@Effedipi wrote:

Hi Donovan,

but I have one question: in SCTL I cannot use delays

Francesco

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If you know precisely how long a single clock cycle is, it's not hard to imagine how to implement delays.... Yes, it's not as "convenient" as just using a "Wait" primitive, but it's most certainly possible and will almost certainly be more reliable and accurate than using a normal while loop.

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P8sWSAS&l=en-CH

[Effedipi]

Thank you all for your help.. I have it clear now.

Francesco